gd32e5/gd32e508/gpioc/
ctl1.rs

1#[doc = "Register `CTL1` reader"]
2pub type R = crate::R<Ctl1Spec>;
3#[doc = "Register `CTL1` writer"]
4pub type W = crate::W<Ctl1Spec>;
5#[doc = "Port x mode bits (x = 8)\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum Md8 {
9    #[doc = "0: Input mode (reset state)"]
10    Input = 0,
11    #[doc = "1: Output mode ,max speed 10MHz"]
12    Speed10m = 1,
13    #[doc = "2: Output mode ,max speed 2MHz"]
14    Speed2m = 2,
15    #[doc = "3: Output mode ,max speed 50MHz"]
16    Speed50m = 3,
17}
18impl From<Md8> for u8 {
19    #[inline(always)]
20    fn from(variant: Md8) -> Self {
21        variant as _
22    }
23}
24impl crate::FieldSpec for Md8 {
25    type Ux = u8;
26}
27#[doc = "Field `MD8` reader - Port x mode bits (x = 8)"]
28pub type Md8R = crate::FieldReader<Md8>;
29impl Md8R {
30    #[doc = "Get enumerated values variant"]
31    #[inline(always)]
32    pub const fn variant(&self) -> Md8 {
33        match self.bits {
34            0 => Md8::Input,
35            1 => Md8::Speed10m,
36            2 => Md8::Speed2m,
37            3 => Md8::Speed50m,
38            _ => unreachable!(),
39        }
40    }
41    #[doc = "Input mode (reset state)"]
42    #[inline(always)]
43    pub fn is_input(&self) -> bool {
44        *self == Md8::Input
45    }
46    #[doc = "Output mode ,max speed 10MHz"]
47    #[inline(always)]
48    pub fn is_speed10m(&self) -> bool {
49        *self == Md8::Speed10m
50    }
51    #[doc = "Output mode ,max speed 2MHz"]
52    #[inline(always)]
53    pub fn is_speed2m(&self) -> bool {
54        *self == Md8::Speed2m
55    }
56    #[doc = "Output mode ,max speed 50MHz"]
57    #[inline(always)]
58    pub fn is_speed50m(&self) -> bool {
59        *self == Md8::Speed50m
60    }
61}
62#[doc = "Field `MD8` writer - Port x mode bits (x = 8)"]
63pub type Md8W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Md8>;
64impl<'a, REG> Md8W<'a, REG>
65where
66    REG: crate::Writable + crate::RegisterSpec,
67    REG::Ux: From<u8>,
68{
69    #[doc = "Input mode (reset state)"]
70    #[inline(always)]
71    pub fn input(self) -> &'a mut crate::W<REG> {
72        self.variant(Md8::Input)
73    }
74    #[doc = "Output mode ,max speed 10MHz"]
75    #[inline(always)]
76    pub fn speed10m(self) -> &'a mut crate::W<REG> {
77        self.variant(Md8::Speed10m)
78    }
79    #[doc = "Output mode ,max speed 2MHz"]
80    #[inline(always)]
81    pub fn speed2m(self) -> &'a mut crate::W<REG> {
82        self.variant(Md8::Speed2m)
83    }
84    #[doc = "Output mode ,max speed 50MHz"]
85    #[inline(always)]
86    pub fn speed50m(self) -> &'a mut crate::W<REG> {
87        self.variant(Md8::Speed50m)
88    }
89}
90#[doc = "Port x configuration bits (x = 8)\n\nValue on reset: 1"]
91#[derive(Clone, Copy, Debug, PartialEq, Eq)]
92#[repr(u8)]
93pub enum Ctl8 {
94    #[doc = "0: Analog mode/GPIO output with push-pull"]
95    AnalogOrPushPull = 0,
96    #[doc = "1: Floating input/GPIO output with open-drain"]
97    FloatingOrOpenDrain = 1,
98    #[doc = "2: Input with pull-up pull-down/AFIO output with push-pull"]
99    InputOrAfioPp = 2,
100    #[doc = "3: Reserved/AFIO output with open-drain"]
101    RsvdorAfioOd = 3,
102}
103impl From<Ctl8> for u8 {
104    #[inline(always)]
105    fn from(variant: Ctl8) -> Self {
106        variant as _
107    }
108}
109impl crate::FieldSpec for Ctl8 {
110    type Ux = u8;
111}
112#[doc = "Field `CTL8` reader - Port x configuration bits (x = 8)"]
113pub type Ctl8R = crate::FieldReader<Ctl8>;
114impl Ctl8R {
115    #[doc = "Get enumerated values variant"]
116    #[inline(always)]
117    pub const fn variant(&self) -> Ctl8 {
118        match self.bits {
119            0 => Ctl8::AnalogOrPushPull,
120            1 => Ctl8::FloatingOrOpenDrain,
121            2 => Ctl8::InputOrAfioPp,
122            3 => Ctl8::RsvdorAfioOd,
123            _ => unreachable!(),
124        }
125    }
126    #[doc = "Analog mode/GPIO output with push-pull"]
127    #[inline(always)]
128    pub fn is_analog_or_push_pull(&self) -> bool {
129        *self == Ctl8::AnalogOrPushPull
130    }
131    #[doc = "Floating input/GPIO output with open-drain"]
132    #[inline(always)]
133    pub fn is_floating_or_open_drain(&self) -> bool {
134        *self == Ctl8::FloatingOrOpenDrain
135    }
136    #[doc = "Input with pull-up pull-down/AFIO output with push-pull"]
137    #[inline(always)]
138    pub fn is_input_or_afio_pp(&self) -> bool {
139        *self == Ctl8::InputOrAfioPp
140    }
141    #[doc = "Reserved/AFIO output with open-drain"]
142    #[inline(always)]
143    pub fn is_rsvdor_afio_od(&self) -> bool {
144        *self == Ctl8::RsvdorAfioOd
145    }
146}
147#[doc = "Field `CTL8` writer - Port x configuration bits (x = 8)"]
148pub type Ctl8W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Ctl8>;
149impl<'a, REG> Ctl8W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152    REG::Ux: From<u8>,
153{
154    #[doc = "Analog mode/GPIO output with push-pull"]
155    #[inline(always)]
156    pub fn analog_or_push_pull(self) -> &'a mut crate::W<REG> {
157        self.variant(Ctl8::AnalogOrPushPull)
158    }
159    #[doc = "Floating input/GPIO output with open-drain"]
160    #[inline(always)]
161    pub fn floating_or_open_drain(self) -> &'a mut crate::W<REG> {
162        self.variant(Ctl8::FloatingOrOpenDrain)
163    }
164    #[doc = "Input with pull-up pull-down/AFIO output with push-pull"]
165    #[inline(always)]
166    pub fn input_or_afio_pp(self) -> &'a mut crate::W<REG> {
167        self.variant(Ctl8::InputOrAfioPp)
168    }
169    #[doc = "Reserved/AFIO output with open-drain"]
170    #[inline(always)]
171    pub fn rsvdor_afio_od(self) -> &'a mut crate::W<REG> {
172        self.variant(Ctl8::RsvdorAfioOd)
173    }
174}
175#[doc = "Field `CTL9` reader - Port x configuration bits (x = 9)"]
176pub use Ctl8R as Ctl9R;
177#[doc = "Field `CTL10` reader - Port x configuration bits (x = 10)"]
178pub use Ctl8R as Ctl10R;
179#[doc = "Field `CTL11` reader - Port x configuration bits (x = 11)"]
180pub use Ctl8R as Ctl11R;
181#[doc = "Field `CTL12` reader - Port x configuration bits (x = 12)"]
182pub use Ctl8R as Ctl12R;
183#[doc = "Field `CTL13` reader - Port x configuration bits (x = 13)"]
184pub use Ctl8R as Ctl13R;
185#[doc = "Field `CTL14` reader - Port x configuration bits (x = 14)"]
186pub use Ctl8R as Ctl14R;
187#[doc = "Field `CTL15` reader - Port x configuration bits (x = 15)"]
188pub use Ctl8R as Ctl15R;
189#[doc = "Field `CTL9` writer - Port x configuration bits (x = 9)"]
190pub use Ctl8W as Ctl9W;
191#[doc = "Field `CTL10` writer - Port x configuration bits (x = 10)"]
192pub use Ctl8W as Ctl10W;
193#[doc = "Field `CTL11` writer - Port x configuration bits (x = 11)"]
194pub use Ctl8W as Ctl11W;
195#[doc = "Field `CTL12` writer - Port x configuration bits (x = 12)"]
196pub use Ctl8W as Ctl12W;
197#[doc = "Field `CTL13` writer - Port x configuration bits (x = 13)"]
198pub use Ctl8W as Ctl13W;
199#[doc = "Field `CTL14` writer - Port x configuration bits (x = 14)"]
200pub use Ctl8W as Ctl14W;
201#[doc = "Field `CTL15` writer - Port x configuration bits (x = 15)"]
202pub use Ctl8W as Ctl15W;
203#[doc = "Field `MD9` reader - Port x mode bits (x = 9)"]
204pub use Md8R as Md9R;
205#[doc = "Field `MD10` reader - Port x mode bits (x = 10 )"]
206pub use Md8R as Md10R;
207#[doc = "Field `MD11` reader - Port x mode bits (x = 11 )"]
208pub use Md8R as Md11R;
209#[doc = "Field `MD12` reader - Port x mode bits (x = 12)"]
210pub use Md8R as Md12R;
211#[doc = "Field `MD13` reader - Port x mode bits (x = 13)"]
212pub use Md8R as Md13R;
213#[doc = "Field `MD14` reader - Port x mode bits (x = 14)"]
214pub use Md8R as Md14R;
215#[doc = "Field `MD15` reader - Port x mode bits (x = 15)"]
216pub use Md8R as Md15R;
217#[doc = "Field `MD9` writer - Port x mode bits (x = 9)"]
218pub use Md8W as Md9W;
219#[doc = "Field `MD10` writer - Port x mode bits (x = 10 )"]
220pub use Md8W as Md10W;
221#[doc = "Field `MD11` writer - Port x mode bits (x = 11 )"]
222pub use Md8W as Md11W;
223#[doc = "Field `MD12` writer - Port x mode bits (x = 12)"]
224pub use Md8W as Md12W;
225#[doc = "Field `MD13` writer - Port x mode bits (x = 13)"]
226pub use Md8W as Md13W;
227#[doc = "Field `MD14` writer - Port x mode bits (x = 14)"]
228pub use Md8W as Md14W;
229#[doc = "Field `MD15` writer - Port x mode bits (x = 15)"]
230pub use Md8W as Md15W;
231impl R {
232    #[doc = "Bits 0:1 - Port x mode bits (x = 8)"]
233    #[inline(always)]
234    pub fn md8(&self) -> Md8R {
235        Md8R::new((self.bits & 3) as u8)
236    }
237    #[doc = "Bits 2:3 - Port x configuration bits (x = 8)"]
238    #[inline(always)]
239    pub fn ctl8(&self) -> Ctl8R {
240        Ctl8R::new(((self.bits >> 2) & 3) as u8)
241    }
242    #[doc = "Bits 4:5 - Port x mode bits (x = 9)"]
243    #[inline(always)]
244    pub fn md9(&self) -> Md9R {
245        Md9R::new(((self.bits >> 4) & 3) as u8)
246    }
247    #[doc = "Bits 6:7 - Port x configuration bits (x = 9)"]
248    #[inline(always)]
249    pub fn ctl9(&self) -> Ctl9R {
250        Ctl9R::new(((self.bits >> 6) & 3) as u8)
251    }
252    #[doc = "Bits 8:9 - Port x mode bits (x = 10 )"]
253    #[inline(always)]
254    pub fn md10(&self) -> Md10R {
255        Md10R::new(((self.bits >> 8) & 3) as u8)
256    }
257    #[doc = "Bits 10:11 - Port x configuration bits (x = 10)"]
258    #[inline(always)]
259    pub fn ctl10(&self) -> Ctl10R {
260        Ctl10R::new(((self.bits >> 10) & 3) as u8)
261    }
262    #[doc = "Bits 12:13 - Port x mode bits (x = 11 )"]
263    #[inline(always)]
264    pub fn md11(&self) -> Md11R {
265        Md11R::new(((self.bits >> 12) & 3) as u8)
266    }
267    #[doc = "Bits 14:15 - Port x configuration bits (x = 11)"]
268    #[inline(always)]
269    pub fn ctl11(&self) -> Ctl11R {
270        Ctl11R::new(((self.bits >> 14) & 3) as u8)
271    }
272    #[doc = "Bits 16:17 - Port x mode bits (x = 12)"]
273    #[inline(always)]
274    pub fn md12(&self) -> Md12R {
275        Md12R::new(((self.bits >> 16) & 3) as u8)
276    }
277    #[doc = "Bits 18:19 - Port x configuration bits (x = 12)"]
278    #[inline(always)]
279    pub fn ctl12(&self) -> Ctl12R {
280        Ctl12R::new(((self.bits >> 18) & 3) as u8)
281    }
282    #[doc = "Bits 20:21 - Port x mode bits (x = 13)"]
283    #[inline(always)]
284    pub fn md13(&self) -> Md13R {
285        Md13R::new(((self.bits >> 20) & 3) as u8)
286    }
287    #[doc = "Bits 22:23 - Port x configuration bits (x = 13)"]
288    #[inline(always)]
289    pub fn ctl13(&self) -> Ctl13R {
290        Ctl13R::new(((self.bits >> 22) & 3) as u8)
291    }
292    #[doc = "Bits 24:25 - Port x mode bits (x = 14)"]
293    #[inline(always)]
294    pub fn md14(&self) -> Md14R {
295        Md14R::new(((self.bits >> 24) & 3) as u8)
296    }
297    #[doc = "Bits 26:27 - Port x configuration bits (x = 14)"]
298    #[inline(always)]
299    pub fn ctl14(&self) -> Ctl14R {
300        Ctl14R::new(((self.bits >> 26) & 3) as u8)
301    }
302    #[doc = "Bits 28:29 - Port x mode bits (x = 15)"]
303    #[inline(always)]
304    pub fn md15(&self) -> Md15R {
305        Md15R::new(((self.bits >> 28) & 3) as u8)
306    }
307    #[doc = "Bits 30:31 - Port x configuration bits (x = 15)"]
308    #[inline(always)]
309    pub fn ctl15(&self) -> Ctl15R {
310        Ctl15R::new(((self.bits >> 30) & 3) as u8)
311    }
312}
313impl W {
314    #[doc = "Bits 0:1 - Port x mode bits (x = 8)"]
315    #[inline(always)]
316    #[must_use]
317    pub fn md8(&mut self) -> Md8W<Ctl1Spec> {
318        Md8W::new(self, 0)
319    }
320    #[doc = "Bits 2:3 - Port x configuration bits (x = 8)"]
321    #[inline(always)]
322    #[must_use]
323    pub fn ctl8(&mut self) -> Ctl8W<Ctl1Spec> {
324        Ctl8W::new(self, 2)
325    }
326    #[doc = "Bits 4:5 - Port x mode bits (x = 9)"]
327    #[inline(always)]
328    #[must_use]
329    pub fn md9(&mut self) -> Md9W<Ctl1Spec> {
330        Md9W::new(self, 4)
331    }
332    #[doc = "Bits 6:7 - Port x configuration bits (x = 9)"]
333    #[inline(always)]
334    #[must_use]
335    pub fn ctl9(&mut self) -> Ctl9W<Ctl1Spec> {
336        Ctl9W::new(self, 6)
337    }
338    #[doc = "Bits 8:9 - Port x mode bits (x = 10 )"]
339    #[inline(always)]
340    #[must_use]
341    pub fn md10(&mut self) -> Md10W<Ctl1Spec> {
342        Md10W::new(self, 8)
343    }
344    #[doc = "Bits 10:11 - Port x configuration bits (x = 10)"]
345    #[inline(always)]
346    #[must_use]
347    pub fn ctl10(&mut self) -> Ctl10W<Ctl1Spec> {
348        Ctl10W::new(self, 10)
349    }
350    #[doc = "Bits 12:13 - Port x mode bits (x = 11 )"]
351    #[inline(always)]
352    #[must_use]
353    pub fn md11(&mut self) -> Md11W<Ctl1Spec> {
354        Md11W::new(self, 12)
355    }
356    #[doc = "Bits 14:15 - Port x configuration bits (x = 11)"]
357    #[inline(always)]
358    #[must_use]
359    pub fn ctl11(&mut self) -> Ctl11W<Ctl1Spec> {
360        Ctl11W::new(self, 14)
361    }
362    #[doc = "Bits 16:17 - Port x mode bits (x = 12)"]
363    #[inline(always)]
364    #[must_use]
365    pub fn md12(&mut self) -> Md12W<Ctl1Spec> {
366        Md12W::new(self, 16)
367    }
368    #[doc = "Bits 18:19 - Port x configuration bits (x = 12)"]
369    #[inline(always)]
370    #[must_use]
371    pub fn ctl12(&mut self) -> Ctl12W<Ctl1Spec> {
372        Ctl12W::new(self, 18)
373    }
374    #[doc = "Bits 20:21 - Port x mode bits (x = 13)"]
375    #[inline(always)]
376    #[must_use]
377    pub fn md13(&mut self) -> Md13W<Ctl1Spec> {
378        Md13W::new(self, 20)
379    }
380    #[doc = "Bits 22:23 - Port x configuration bits (x = 13)"]
381    #[inline(always)]
382    #[must_use]
383    pub fn ctl13(&mut self) -> Ctl13W<Ctl1Spec> {
384        Ctl13W::new(self, 22)
385    }
386    #[doc = "Bits 24:25 - Port x mode bits (x = 14)"]
387    #[inline(always)]
388    #[must_use]
389    pub fn md14(&mut self) -> Md14W<Ctl1Spec> {
390        Md14W::new(self, 24)
391    }
392    #[doc = "Bits 26:27 - Port x configuration bits (x = 14)"]
393    #[inline(always)]
394    #[must_use]
395    pub fn ctl14(&mut self) -> Ctl14W<Ctl1Spec> {
396        Ctl14W::new(self, 26)
397    }
398    #[doc = "Bits 28:29 - Port x mode bits (x = 15)"]
399    #[inline(always)]
400    #[must_use]
401    pub fn md15(&mut self) -> Md15W<Ctl1Spec> {
402        Md15W::new(self, 28)
403    }
404    #[doc = "Bits 30:31 - Port x configuration bits (x = 15)"]
405    #[inline(always)]
406    #[must_use]
407    pub fn ctl15(&mut self) -> Ctl15W<Ctl1Spec> {
408        Ctl15W::new(self, 30)
409    }
410}
411#[doc = "port control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
412pub struct Ctl1Spec;
413impl crate::RegisterSpec for Ctl1Spec {
414    type Ux = u32;
415}
416#[doc = "`read()` method returns [`ctl1::R`](R) reader structure"]
417impl crate::Readable for Ctl1Spec {}
418#[doc = "`write(|w| ..)` method takes [`ctl1::W`](W) writer structure"]
419impl crate::Writable for Ctl1Spec {
420    type Safety = crate::Unsafe;
421    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
422    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
423}
424#[doc = "`reset()` method sets CTL1 to value 0x4444_4444"]
425impl crate::Resettable for Ctl1Spec {
426    const RESET_VALUE: u32 = 0x4444_4444;
427}
gd32e5/gd32e508/gpioc/ctl1.rs

gd32e5/gd32e508/gpioc/
ctl1.rs
