Struct gd32e1::gd32e103::rcu::RegisterBlock

#[repr(C)]
pub struct RegisterBlock { /* private fields */ }

Register block

Implementations

impl RegisterBlock

pub const fn ctl0(&self) -> &Ctl0

0x00 - Control register

pub const fn cfg0(&self) -> &Cfg0

0x04 - Clock configuration register 0 (RCU_CFG0)

pub const fn int(&self) -> &Int

0x08 - Clock interrupt register (RCU_INT)

pub const fn apb2rst(&self) -> &Apb2rst

0x0c - APB2 reset register (RCU_APB2RST)

pub const fn apb1rst(&self) -> &Apb1rst

0x10 - APB1 reset register (RCU_APB1RST)

pub const fn ahben(&self) -> &Ahben

0x14 - AHB enable register

pub const fn apb2en(&self) -> &Apb2en

0x18 - APB2 clock enable register (RCU_APB2EN)

pub const fn apb1en(&self) -> &Apb1en

0x1c - APB1 clock enable register (RCU_APB1EN)

pub const fn bdctl(&self) -> &Bdctl

0x20 - Backup domain control register (RCU_BDCTL)

pub const fn rstsck(&self) -> &Rstsck

0x24 - Reset source /clock register (RCU_RSTSCK)

pub const fn ahbrst(&self) -> &Ahbrst

0x28 - AHB reset register

pub const fn cfg1(&self) -> &Cfg1

0x2c - Clock Configuration register 1

pub const fn dsv(&self) -> &Dsv

0x34 - Deep sleep mode Voltage register

pub const fn addctl(&self) -> &Addctl

0xc0 - Additional clock control register

pub const fn addint(&self) -> &Addint

0xcc - Additional clock interrupt register

pub const fn addapb1rst(&self) -> &Addapb1rst

0xe0 - APB1 additional reset register

pub const fn addapb1en(&self) -> &Addapb1en

0xe4 - APB1 additional enable register