Type Alias gd32e1::gd32e103::gpioa::ctl0::W

pub type W = W<Ctl0Spec>;

Register CTL0 writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn md0(&mut self) -> Md0W<'_, Ctl0Spec>

Bits 0:1 - Port x mode bits (x = 0)

pub fn ctl0(&mut self) -> Ctl0W<'_, Ctl0Spec>

Bits 2:3 - Port x configuration bits (x = 0)

pub fn md1(&mut self) -> Md1W<'_, Ctl0Spec>

Bits 4:5 - Port x mode bits (x = 1)

pub fn ctl1(&mut self) -> Ctl1W<'_, Ctl0Spec>

Bits 6:7 - Port x configuration bits (x = 1)

pub fn md2(&mut self) -> Md2W<'_, Ctl0Spec>

Bits 8:9 - Port x mode bits (x = 2 )

pub fn ctl2(&mut self) -> Ctl2W<'_, Ctl0Spec>

Bits 10:11 - Port x configuration bits (x = 2)

pub fn md3(&mut self) -> Md3W<'_, Ctl0Spec>

Bits 12:13 - Port x mode bits (x = 3 )

pub fn ctl3(&mut self) -> Ctl3W<'_, Ctl0Spec>

Bits 14:15 - Port x configuration bits (x = 3)

pub fn md4(&mut self) -> Md4W<'_, Ctl0Spec>

Bits 16:17 - Port x mode bits (x = 4)

pub fn ctl4(&mut self) -> Ctl4W<'_, Ctl0Spec>

Bits 18:19 - Port x configuration bits (x = 4)

pub fn md5(&mut self) -> Md5W<'_, Ctl0Spec>

Bits 20:21 - Port x mode bits (x = 5)

pub fn ctl5(&mut self) -> Ctl5W<'_, Ctl0Spec>

Bits 22:23 - Port x configuration bits (x = 5)

pub fn md6(&mut self) -> Md6W<'_, Ctl0Spec>

Bits 24:25 - Port x mode bits (x = 6)

pub fn ctl6(&mut self) -> Ctl6W<'_, Ctl0Spec>

Bits 26:27 - Port x configuration bits (x = 6)

pub fn md7(&mut self) -> Md7W<'_, Ctl0Spec>

Bits 28:29 - Port x mode bits (x = 7)

pub fn ctl7(&mut self) -> Ctl7W<'_, Ctl0Spec>

Bits 30:31 - Port x configuration bits (x = 7)