pub type W = W<Ch4ctlSpec>;
Expand description
Register CH4CTL
writer
Aliased Type§
struct W { /* private fields */ }
Implementations§
source§impl W
impl W
sourcepub fn chen(&mut self) -> ChenW<'_, Ch4ctlSpec>
pub fn chen(&mut self) -> ChenW<'_, Ch4ctlSpec>
Bit 0 - Channel enable
sourcepub fn ftfie(&mut self) -> FtfieW<'_, Ch4ctlSpec>
pub fn ftfie(&mut self) -> FtfieW<'_, Ch4ctlSpec>
Bit 1 - Enable bit for channel full transfer finish interrupt
sourcepub fn htfie(&mut self) -> HtfieW<'_, Ch4ctlSpec>
pub fn htfie(&mut self) -> HtfieW<'_, Ch4ctlSpec>
Bit 2 - Enable bit for channel half transfer finish interrupt
sourcepub fn errie(&mut self) -> ErrieW<'_, Ch4ctlSpec>
pub fn errie(&mut self) -> ErrieW<'_, Ch4ctlSpec>
Bit 3 - Enable bit for channel error interrupt
sourcepub fn dir(&mut self) -> DirW<'_, Ch4ctlSpec>
pub fn dir(&mut self) -> DirW<'_, Ch4ctlSpec>
Bit 4 - Transfer direction
sourcepub fn cmen(&mut self) -> CmenW<'_, Ch4ctlSpec>
pub fn cmen(&mut self) -> CmenW<'_, Ch4ctlSpec>
Bit 5 - Circular mode enable
sourcepub fn pnaga(&mut self) -> PnagaW<'_, Ch4ctlSpec>
pub fn pnaga(&mut self) -> PnagaW<'_, Ch4ctlSpec>
Bit 6 - Next address generation algorithm of peripheral
sourcepub fn mnaga(&mut self) -> MnagaW<'_, Ch4ctlSpec>
pub fn mnaga(&mut self) -> MnagaW<'_, Ch4ctlSpec>
Bit 7 - Next address generation algorithm of memory
sourcepub fn pwidth(&mut self) -> PwidthW<'_, Ch4ctlSpec>
pub fn pwidth(&mut self) -> PwidthW<'_, Ch4ctlSpec>
Bits 8:9 - Transfer data size of peripheral
sourcepub fn mwidth(&mut self) -> MwidthW<'_, Ch4ctlSpec>
pub fn mwidth(&mut self) -> MwidthW<'_, Ch4ctlSpec>
Bits 10:11 - Transfer data size of memory
sourcepub fn prio(&mut self) -> PrioW<'_, Ch4ctlSpec>
pub fn prio(&mut self) -> PrioW<'_, Ch4ctlSpec>
Bits 12:13 - Priority level
sourcepub fn m2m(&mut self) -> M2mW<'_, Ch4ctlSpec>
pub fn m2m(&mut self) -> M2mW<'_, Ch4ctlSpec>
Bit 14 - Memory to memory mode