gd32c1/gd32c103/timer0/
ctl0.rs

1#[doc = "Register `CTL0` reader"]
2pub type R = crate::R<Ctl0Spec>;
3#[doc = "Register `CTL0` writer"]
4pub type W = crate::W<Ctl0Spec>;
5#[doc = "Counter enable\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum Cen {
8    #[doc = "0: Counter disabled"]
9    Disabled = 0,
10    #[doc = "1: Counter enabled"]
11    Enabled = 1,
12}
13impl From<Cen> for bool {
14    #[inline(always)]
15    fn from(variant: Cen) -> Self {
16        variant as u8 != 0
17    }
18}
19#[doc = "Field `CEN` reader - Counter enable"]
20pub type CenR = crate::BitReader<Cen>;
21impl CenR {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> Cen {
25        match self.bits {
26            false => Cen::Disabled,
27            true => Cen::Enabled,
28        }
29    }
30    #[doc = "Counter disabled"]
31    #[inline(always)]
32    pub fn is_disabled(&self) -> bool {
33        *self == Cen::Disabled
34    }
35    #[doc = "Counter enabled"]
36    #[inline(always)]
37    pub fn is_enabled(&self) -> bool {
38        *self == Cen::Enabled
39    }
40}
41#[doc = "Field `CEN` writer - Counter enable"]
42pub type CenW<'a, REG> = crate::BitWriter<'a, REG, Cen>;
43impl<'a, REG> CenW<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Counter disabled"]
48    #[inline(always)]
49    pub fn disabled(self) -> &'a mut crate::W<REG> {
50        self.variant(Cen::Disabled)
51    }
52    #[doc = "Counter enabled"]
53    #[inline(always)]
54    pub fn enabled(self) -> &'a mut crate::W<REG> {
55        self.variant(Cen::Enabled)
56    }
57}
58#[doc = "Update disable\n\nValue on reset: 0"]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60pub enum Updis {
61    #[doc = "0: Update event enabled"]
62    Enabled = 0,
63    #[doc = "1: Update event disabled"]
64    Disabled = 1,
65}
66impl From<Updis> for bool {
67    #[inline(always)]
68    fn from(variant: Updis) -> Self {
69        variant as u8 != 0
70    }
71}
72#[doc = "Field `UPDIS` reader - Update disable"]
73pub type UpdisR = crate::BitReader<Updis>;
74impl UpdisR {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> Updis {
78        match self.bits {
79            false => Updis::Enabled,
80            true => Updis::Disabled,
81        }
82    }
83    #[doc = "Update event enabled"]
84    #[inline(always)]
85    pub fn is_enabled(&self) -> bool {
86        *self == Updis::Enabled
87    }
88    #[doc = "Update event disabled"]
89    #[inline(always)]
90    pub fn is_disabled(&self) -> bool {
91        *self == Updis::Disabled
92    }
93}
94#[doc = "Field `UPDIS` writer - Update disable"]
95pub type UpdisW<'a, REG> = crate::BitWriter<'a, REG, Updis>;
96impl<'a, REG> UpdisW<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "Update event enabled"]
101    #[inline(always)]
102    pub fn enabled(self) -> &'a mut crate::W<REG> {
103        self.variant(Updis::Enabled)
104    }
105    #[doc = "Update event disabled"]
106    #[inline(always)]
107    pub fn disabled(self) -> &'a mut crate::W<REG> {
108        self.variant(Updis::Disabled)
109    }
110}
111#[doc = "Update source\n\nValue on reset: 0"]
112#[derive(Clone, Copy, Debug, PartialEq, Eq)]
113pub enum Ups {
114    #[doc = "0: Any of counter overflow/underflow, setting UPG, or update through slave mode, generates an update interrupt or DMA request"]
115    AnyEvent = 0,
116    #[doc = "1: Only counter overflow/underflow generates an update interrupt or DMA request"]
117    CounterOnly = 1,
118}
119impl From<Ups> for bool {
120    #[inline(always)]
121    fn from(variant: Ups) -> Self {
122        variant as u8 != 0
123    }
124}
125#[doc = "Field `UPS` reader - Update source"]
126pub type UpsR = crate::BitReader<Ups>;
127impl UpsR {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> Ups {
131        match self.bits {
132            false => Ups::AnyEvent,
133            true => Ups::CounterOnly,
134        }
135    }
136    #[doc = "Any of counter overflow/underflow, setting UPG, or update through slave mode, generates an update interrupt or DMA request"]
137    #[inline(always)]
138    pub fn is_any_event(&self) -> bool {
139        *self == Ups::AnyEvent
140    }
141    #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"]
142    #[inline(always)]
143    pub fn is_counter_only(&self) -> bool {
144        *self == Ups::CounterOnly
145    }
146}
147#[doc = "Field `UPS` writer - Update source"]
148pub type UpsW<'a, REG> = crate::BitWriter<'a, REG, Ups>;
149impl<'a, REG> UpsW<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "Any of counter overflow/underflow, setting UPG, or update through slave mode, generates an update interrupt or DMA request"]
154    #[inline(always)]
155    pub fn any_event(self) -> &'a mut crate::W<REG> {
156        self.variant(Ups::AnyEvent)
157    }
158    #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"]
159    #[inline(always)]
160    pub fn counter_only(self) -> &'a mut crate::W<REG> {
161        self.variant(Ups::CounterOnly)
162    }
163}
164#[doc = "Single pulse mode\n\nValue on reset: 0"]
165#[derive(Clone, Copy, Debug, PartialEq, Eq)]
166pub enum Spm {
167    #[doc = "0: Counter is not stopped at update event"]
168    Disabled = 0,
169    #[doc = "1: Counter stops counting at the next update event (clearing the CEN bit)"]
170    Enabled = 1,
171}
172impl From<Spm> for bool {
173    #[inline(always)]
174    fn from(variant: Spm) -> Self {
175        variant as u8 != 0
176    }
177}
178#[doc = "Field `SPM` reader - Single pulse mode"]
179pub type SpmR = crate::BitReader<Spm>;
180impl SpmR {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> Spm {
184        match self.bits {
185            false => Spm::Disabled,
186            true => Spm::Enabled,
187        }
188    }
189    #[doc = "Counter is not stopped at update event"]
190    #[inline(always)]
191    pub fn is_disabled(&self) -> bool {
192        *self == Spm::Disabled
193    }
194    #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"]
195    #[inline(always)]
196    pub fn is_enabled(&self) -> bool {
197        *self == Spm::Enabled
198    }
199}
200#[doc = "Field `SPM` writer - Single pulse mode"]
201pub type SpmW<'a, REG> = crate::BitWriter<'a, REG, Spm>;
202impl<'a, REG> SpmW<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    #[doc = "Counter is not stopped at update event"]
207    #[inline(always)]
208    pub fn disabled(self) -> &'a mut crate::W<REG> {
209        self.variant(Spm::Disabled)
210    }
211    #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"]
212    #[inline(always)]
213    pub fn enabled(self) -> &'a mut crate::W<REG> {
214        self.variant(Spm::Enabled)
215    }
216}
217#[doc = "Direction\n\nValue on reset: 0"]
218#[derive(Clone, Copy, Debug, PartialEq, Eq)]
219pub enum Dir {
220    #[doc = "0: Counter used as upcounter"]
221    Up = 0,
222    #[doc = "1: Counter used as downcounter"]
223    Down = 1,
224}
225impl From<Dir> for bool {
226    #[inline(always)]
227    fn from(variant: Dir) -> Self {
228        variant as u8 != 0
229    }
230}
231#[doc = "Field `DIR` reader - Direction"]
232pub type DirR = crate::BitReader<Dir>;
233impl DirR {
234    #[doc = "Get enumerated values variant"]
235    #[inline(always)]
236    pub const fn variant(&self) -> Dir {
237        match self.bits {
238            false => Dir::Up,
239            true => Dir::Down,
240        }
241    }
242    #[doc = "Counter used as upcounter"]
243    #[inline(always)]
244    pub fn is_up(&self) -> bool {
245        *self == Dir::Up
246    }
247    #[doc = "Counter used as downcounter"]
248    #[inline(always)]
249    pub fn is_down(&self) -> bool {
250        *self == Dir::Down
251    }
252}
253#[doc = "Field `DIR` writer - Direction"]
254pub type DirW<'a, REG> = crate::BitWriter<'a, REG, Dir>;
255impl<'a, REG> DirW<'a, REG>
256where
257    REG: crate::Writable + crate::RegisterSpec,
258{
259    #[doc = "Counter used as upcounter"]
260    #[inline(always)]
261    pub fn up(self) -> &'a mut crate::W<REG> {
262        self.variant(Dir::Up)
263    }
264    #[doc = "Counter used as downcounter"]
265    #[inline(always)]
266    pub fn down(self) -> &'a mut crate::W<REG> {
267        self.variant(Dir::Down)
268    }
269}
270#[doc = "Counter aligns mode selection\n\nValue on reset: 0"]
271#[derive(Clone, Copy, Debug, PartialEq, Eq)]
272#[repr(u8)]
273pub enum Cam {
274    #[doc = "0: The counter counts up or down depending on the direction bit"]
275    EdgeAligned = 0,
276    #[doc = "1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down."]
277    CenterAlignedCountingDown = 1,
278    #[doc = "2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up."]
279    CenterAlignedCountingUp = 2,
280    #[doc = "3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down."]
281    CenterAlignedCountingUpDown = 3,
282}
283impl From<Cam> for u8 {
284    #[inline(always)]
285    fn from(variant: Cam) -> Self {
286        variant as _
287    }
288}
289impl crate::FieldSpec for Cam {
290    type Ux = u8;
291}
292#[doc = "Field `CAM` reader - Counter aligns mode selection"]
293pub type CamR = crate::FieldReader<Cam>;
294impl CamR {
295    #[doc = "Get enumerated values variant"]
296    #[inline(always)]
297    pub const fn variant(&self) -> Cam {
298        match self.bits {
299            0 => Cam::EdgeAligned,
300            1 => Cam::CenterAlignedCountingDown,
301            2 => Cam::CenterAlignedCountingUp,
302            3 => Cam::CenterAlignedCountingUpDown,
303            _ => unreachable!(),
304        }
305    }
306    #[doc = "The counter counts up or down depending on the direction bit"]
307    #[inline(always)]
308    pub fn is_edge_aligned(&self) -> bool {
309        *self == Cam::EdgeAligned
310    }
311    #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down."]
312    #[inline(always)]
313    pub fn is_center_aligned_counting_down(&self) -> bool {
314        *self == Cam::CenterAlignedCountingDown
315    }
316    #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up."]
317    #[inline(always)]
318    pub fn is_center_aligned_counting_up(&self) -> bool {
319        *self == Cam::CenterAlignedCountingUp
320    }
321    #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down."]
322    #[inline(always)]
323    pub fn is_center_aligned_counting_up_down(&self) -> bool {
324        *self == Cam::CenterAlignedCountingUpDown
325    }
326}
327#[doc = "Field `CAM` writer - Counter aligns mode selection"]
328pub type CamW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Cam>;
329impl<'a, REG> CamW<'a, REG>
330where
331    REG: crate::Writable + crate::RegisterSpec,
332    REG::Ux: From<u8>,
333{
334    #[doc = "The counter counts up or down depending on the direction bit"]
335    #[inline(always)]
336    pub fn edge_aligned(self) -> &'a mut crate::W<REG> {
337        self.variant(Cam::EdgeAligned)
338    }
339    #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down."]
340    #[inline(always)]
341    pub fn center_aligned_counting_down(self) -> &'a mut crate::W<REG> {
342        self.variant(Cam::CenterAlignedCountingDown)
343    }
344    #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up."]
345    #[inline(always)]
346    pub fn center_aligned_counting_up(self) -> &'a mut crate::W<REG> {
347        self.variant(Cam::CenterAlignedCountingUp)
348    }
349    #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down."]
350    #[inline(always)]
351    pub fn center_aligned_counting_up_down(self) -> &'a mut crate::W<REG> {
352        self.variant(Cam::CenterAlignedCountingUpDown)
353    }
354}
355#[doc = "Auto-reload shadow enable\n\nValue on reset: 0"]
356#[derive(Clone, Copy, Debug, PartialEq, Eq)]
357pub enum Arse {
358    #[doc = "0: The shadow register for CAR is disabled"]
359    Disabled = 0,
360    #[doc = "1: The shadow register for CAR is enabled"]
361    Enabled = 1,
362}
363impl From<Arse> for bool {
364    #[inline(always)]
365    fn from(variant: Arse) -> Self {
366        variant as u8 != 0
367    }
368}
369#[doc = "Field `ARSE` reader - Auto-reload shadow enable"]
370pub type ArseR = crate::BitReader<Arse>;
371impl ArseR {
372    #[doc = "Get enumerated values variant"]
373    #[inline(always)]
374    pub const fn variant(&self) -> Arse {
375        match self.bits {
376            false => Arse::Disabled,
377            true => Arse::Enabled,
378        }
379    }
380    #[doc = "The shadow register for CAR is disabled"]
381    #[inline(always)]
382    pub fn is_disabled(&self) -> bool {
383        *self == Arse::Disabled
384    }
385    #[doc = "The shadow register for CAR is enabled"]
386    #[inline(always)]
387    pub fn is_enabled(&self) -> bool {
388        *self == Arse::Enabled
389    }
390}
391#[doc = "Field `ARSE` writer - Auto-reload shadow enable"]
392pub type ArseW<'a, REG> = crate::BitWriter<'a, REG, Arse>;
393impl<'a, REG> ArseW<'a, REG>
394where
395    REG: crate::Writable + crate::RegisterSpec,
396{
397    #[doc = "The shadow register for CAR is disabled"]
398    #[inline(always)]
399    pub fn disabled(self) -> &'a mut crate::W<REG> {
400        self.variant(Arse::Disabled)
401    }
402    #[doc = "The shadow register for CAR is enabled"]
403    #[inline(always)]
404    pub fn enabled(self) -> &'a mut crate::W<REG> {
405        self.variant(Arse::Enabled)
406    }
407}
408#[doc = "Clock division\n\nValue on reset: 0"]
409#[derive(Clone, Copy, Debug, PartialEq, Eq)]
410#[repr(u8)]
411pub enum Ckdiv {
412    #[doc = "0: t_DTS = t_CK_INT"]
413    Div1 = 0,
414    #[doc = "1: t_DTS = 2 × t_CK_INT"]
415    Div2 = 1,
416    #[doc = "2: t_DTS = 4 × t_CK_INT"]
417    Div4 = 2,
418}
419impl From<Ckdiv> for u8 {
420    #[inline(always)]
421    fn from(variant: Ckdiv) -> Self {
422        variant as _
423    }
424}
425impl crate::FieldSpec for Ckdiv {
426    type Ux = u8;
427}
428#[doc = "Field `CKDIV` reader - Clock division"]
429pub type CkdivR = crate::FieldReader<Ckdiv>;
430impl CkdivR {
431    #[doc = "Get enumerated values variant"]
432    #[inline(always)]
433    pub const fn variant(&self) -> Option<Ckdiv> {
434        match self.bits {
435            0 => Some(Ckdiv::Div1),
436            1 => Some(Ckdiv::Div2),
437            2 => Some(Ckdiv::Div4),
438            _ => None,
439        }
440    }
441    #[doc = "t_DTS = t_CK_INT"]
442    #[inline(always)]
443    pub fn is_div1(&self) -> bool {
444        *self == Ckdiv::Div1
445    }
446    #[doc = "t_DTS = 2 × t_CK_INT"]
447    #[inline(always)]
448    pub fn is_div2(&self) -> bool {
449        *self == Ckdiv::Div2
450    }
451    #[doc = "t_DTS = 4 × t_CK_INT"]
452    #[inline(always)]
453    pub fn is_div4(&self) -> bool {
454        *self == Ckdiv::Div4
455    }
456}
457#[doc = "Field `CKDIV` writer - Clock division"]
458pub type CkdivW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ckdiv>;
459impl<'a, REG> CkdivW<'a, REG>
460where
461    REG: crate::Writable + crate::RegisterSpec,
462    REG::Ux: From<u8>,
463{
464    #[doc = "t_DTS = t_CK_INT"]
465    #[inline(always)]
466    pub fn div1(self) -> &'a mut crate::W<REG> {
467        self.variant(Ckdiv::Div1)
468    }
469    #[doc = "t_DTS = 2 × t_CK_INT"]
470    #[inline(always)]
471    pub fn div2(self) -> &'a mut crate::W<REG> {
472        self.variant(Ckdiv::Div2)
473    }
474    #[doc = "t_DTS = 4 × t_CK_INT"]
475    #[inline(always)]
476    pub fn div4(self) -> &'a mut crate::W<REG> {
477        self.variant(Ckdiv::Div4)
478    }
479}
480impl R {
481    #[doc = "Bit 0 - Counter enable"]
482    #[inline(always)]
483    pub fn cen(&self) -> CenR {
484        CenR::new((self.bits & 1) != 0)
485    }
486    #[doc = "Bit 1 - Update disable"]
487    #[inline(always)]
488    pub fn updis(&self) -> UpdisR {
489        UpdisR::new(((self.bits >> 1) & 1) != 0)
490    }
491    #[doc = "Bit 2 - Update source"]
492    #[inline(always)]
493    pub fn ups(&self) -> UpsR {
494        UpsR::new(((self.bits >> 2) & 1) != 0)
495    }
496    #[doc = "Bit 3 - Single pulse mode"]
497    #[inline(always)]
498    pub fn spm(&self) -> SpmR {
499        SpmR::new(((self.bits >> 3) & 1) != 0)
500    }
501    #[doc = "Bit 4 - Direction"]
502    #[inline(always)]
503    pub fn dir(&self) -> DirR {
504        DirR::new(((self.bits >> 4) & 1) != 0)
505    }
506    #[doc = "Bits 5:6 - Counter aligns mode selection"]
507    #[inline(always)]
508    pub fn cam(&self) -> CamR {
509        CamR::new(((self.bits >> 5) & 3) as u8)
510    }
511    #[doc = "Bit 7 - Auto-reload shadow enable"]
512    #[inline(always)]
513    pub fn arse(&self) -> ArseR {
514        ArseR::new(((self.bits >> 7) & 1) != 0)
515    }
516    #[doc = "Bits 8:9 - Clock division"]
517    #[inline(always)]
518    pub fn ckdiv(&self) -> CkdivR {
519        CkdivR::new(((self.bits >> 8) & 3) as u8)
520    }
521}
522impl W {
523    #[doc = "Bit 0 - Counter enable"]
524    #[inline(always)]
525    #[must_use]
526    pub fn cen(&mut self) -> CenW<Ctl0Spec> {
527        CenW::new(self, 0)
528    }
529    #[doc = "Bit 1 - Update disable"]
530    #[inline(always)]
531    #[must_use]
532    pub fn updis(&mut self) -> UpdisW<Ctl0Spec> {
533        UpdisW::new(self, 1)
534    }
535    #[doc = "Bit 2 - Update source"]
536    #[inline(always)]
537    #[must_use]
538    pub fn ups(&mut self) -> UpsW<Ctl0Spec> {
539        UpsW::new(self, 2)
540    }
541    #[doc = "Bit 3 - Single pulse mode"]
542    #[inline(always)]
543    #[must_use]
544    pub fn spm(&mut self) -> SpmW<Ctl0Spec> {
545        SpmW::new(self, 3)
546    }
547    #[doc = "Bit 4 - Direction"]
548    #[inline(always)]
549    #[must_use]
550    pub fn dir(&mut self) -> DirW<Ctl0Spec> {
551        DirW::new(self, 4)
552    }
553    #[doc = "Bits 5:6 - Counter aligns mode selection"]
554    #[inline(always)]
555    #[must_use]
556    pub fn cam(&mut self) -> CamW<Ctl0Spec> {
557        CamW::new(self, 5)
558    }
559    #[doc = "Bit 7 - Auto-reload shadow enable"]
560    #[inline(always)]
561    #[must_use]
562    pub fn arse(&mut self) -> ArseW<Ctl0Spec> {
563        ArseW::new(self, 7)
564    }
565    #[doc = "Bits 8:9 - Clock division"]
566    #[inline(always)]
567    #[must_use]
568    pub fn ckdiv(&mut self) -> CkdivW<Ctl0Spec> {
569        CkdivW::new(self, 8)
570    }
571}
572#[doc = "control register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
573pub struct Ctl0Spec;
574impl crate::RegisterSpec for Ctl0Spec {
575    type Ux = u32;
576}
577#[doc = "`read()` method returns [`ctl0::R`](R) reader structure"]
578impl crate::Readable for Ctl0Spec {}
579#[doc = "`write(|w| ..)` method takes [`ctl0::W`](W) writer structure"]
580impl crate::Writable for Ctl0Spec {
581    type Safety = crate::Unsafe;
582    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
583    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
584}
585#[doc = "`reset()` method sets CTL0 to value 0"]
586impl crate::Resettable for Ctl0Spec {
587    const RESET_VALUE: u32 = 0;
588}
gd32c1/gd32c103/timer0/ctl0.rs

gd32c1/gd32c103/timer0/
ctl0.rs
