gcn_assembler/instructions/
mod.rs

1//! GCN instructions for AMD GPUs.
2
3use serde::{Deserialize, Serialize};
4
5/// GCN register
6#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
7pub enum GcnReg {
8    /// Vector general purpose register
9    VGPR(u8),
10    /// Scalar general purpose register
11    SGPR(u8),
12    /// Accumulation register
13    AGPR(u8),
14}
15
16impl std::fmt::Display for GcnReg {
17    fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
18        match self {
19            GcnReg::VGPR(n) => write!(f, "v{}", n),
20            GcnReg::SGPR(n) => write!(f, "s{}", n),
21            GcnReg::AGPR(n) => write!(f, "a{}", n),
22        }
23    }
24}
25
26/// GCN instruction set (CDNA/RDNA base)
27#[derive(Debug, Clone, PartialEq, Serialize, Deserialize)]
28pub enum GcnInstruction {
29    /// Arithmetic: v_add_f32 dst, src0, src1
30    VAddF32 { dst: GcnReg, src0: GcnReg, src1: GcnReg },
31    /// Arithmetic: v_mul_f32 dst, src0, src1
32    VMulF32 { dst: GcnReg, src0: GcnReg, src1: GcnReg },
33    /// Arithmetic: v_dot2_f32_f16 dst, src0, src1
34    VDot2F32F16 { dst: GcnReg, src0: GcnReg, src1: GcnReg },
35    /// Memory: global_load_dword dst, addr, off
36    GlobalLoadDword { dst: GcnReg, addr: GcnReg, offset: u16 },
37    /// Memory: global_store_dword addr, src, off
38    GlobalStoreDword { addr: GcnReg, src: GcnReg, offset: u16 },
39    /// Control flow: s_endpgm
40    SEndPgm,
41    /// Control flow: s_nop
42    SNop(u16),
43}
gcn_assembler/instructions/mod.rs

gcn_assembler/instructions/
mod.rs
