fusb302b/registers.rs
1//! FUSB302B registers
2//!
3//! Setters/getters/clearers generated using macros, `Default` for each register is its reset value.
4
5use {
6 crate::DEVICE_ADDRESS,
7 defmt::Format,
8 embedded_hal::blocking::i2c::{Write, WriteRead},
9 proc_bitfield::bitfield,
10 usb_pd::{DataRole, PowerRole},
11};
12
13pub struct Registers<I2C> {
14 i2c: I2C,
15}
16
17macro_rules! generate_register_read {
18 ($reg:ident, $fn:ident) => {
19 pub fn $fn(&mut self) -> $reg {
20 self.read_register_raw(Register::$reg as u8).into()
21 }
22 };
23}
24
25macro_rules! generate_register_write {
26 ($reg:ident, $fn:ident) => {
27 paste::item! {
28 pub fn [<set_ $fn>](&mut self, value: $reg) {
29 self.write_register_raw(Register::$reg as u8, value.0);
30 }
31 }
32 };
33}
34
35macro_rules! generate_register_clear {
36 ($reg:ident, $fn:ident) => {
37 paste::item! {
38 pub fn [<clear_ $fn>](&mut self) {
39 self.write_register_raw(Register::$reg as u8, $reg::default().0);
40 }
41 }
42 };
43}
44
45macro_rules! generate_register_accessors {
46 () => {};
47
48 (($reg:ident, $fn:ident, r), $($tail:tt)*) => {
49 generate_register_read!($reg, $fn);
50
51 generate_register_accessors!($($tail)*);
52 };
53
54 (($reg:ident, $fn:ident, rw), $($tail:tt)*) => {
55 generate_register_read!($reg, $fn);
56 generate_register_write!($reg, $fn);
57
58 generate_register_accessors!($($tail)*);
59 };
60
61 (($reg:ident, $fn:ident, wc), $($tail:tt)*) => {
62 generate_register_write!($reg, $fn);
63 generate_register_clear!($reg, $fn);
64
65 generate_register_accessors!($($tail)*);
66 };
67
68 (($reg:ident, $fn:ident, rc), $($tail:tt)*) => {
69 generate_register_read!($reg, $fn);
70 generate_register_clear!($reg, $fn);
71
72 generate_register_accessors!($($tail)*);
73 };
74
75 (($reg:ident, $fn:ident, rwc), $($tail:tt)*) => {
76 generate_register_read!($reg, $fn);
77 generate_register_write!($reg, $fn);
78 generate_register_clear!($reg, $fn);
79
80 generate_register_accessors!($($tail)*);
81 };
82}
83
84impl<I2C: Write + WriteRead> Registers<I2C> {
85 pub fn new(i2c: I2C) -> Self {
86 Self { i2c }
87 }
88
89 fn write_register_raw(&mut self, register: u8, value: u8) {
90 assert!(self.i2c.write(DEVICE_ADDRESS, &[register, value]).is_ok());
91 }
92
93 fn read_register_raw(&mut self, register: u8) -> u8 {
94 let mut buffer = [0u8];
95 assert!(self
96 .i2c
97 .write_read(DEVICE_ADDRESS, &[register], &mut buffer)
98 .is_ok());
99 buffer[0]
100 }
101
102 pub fn read_fifo(&mut self, buf: &mut [u8]) {
103 assert!(self
104 .i2c
105 .write_read(DEVICE_ADDRESS, &[Register::Fifo as u8], buf)
106 .is_ok());
107 }
108
109 pub fn write_raw(&mut self, buf: &mut [u8]) {
110 assert!(self.i2c.write(DEVICE_ADDRESS, buf).is_ok());
111 }
112
113 generate_register_accessors!(
114 (DeviceId, device_id, r),
115 (Switches0, switches0, rw),
116 (Switches1, switches1, rw),
117 (Measure, measure, rw),
118 (Slice, slice, rw),
119 (Control0, control0, rwc),
120 (Control1, control1, rwc),
121 (Control2, control2, rw),
122 (Control3, control3, rw),
123 (Mask1, mask1, rw),
124 (Power, power, rw),
125 (Reset, reset, wc),
126 (OcPreg, ocpreg, rw),
127 (MaskA, mask_a, rw),
128 (MaskB, mask_b, rw),
129 (Control4, control4, rw),
130 (Status0A, status0a, r),
131 (Status1A, status1a, r),
132 (InterruptA, interrupta, rc),
133 (InterruptB, interruptb, rc),
134 (Status0, status0, r),
135 (Status1, status1, r),
136 (Interrupt, interrupt, rc),
137 );
138}
139
140pub enum Register {
141 DeviceId = 0x01,
142 Switches0 = 0x02,
143 Switches1 = 0x03,
144 Measure = 0x04,
145 Slice = 0x05,
146 Control0 = 0x06,
147 Control1 = 0x07,
148 Control2 = 0x08,
149 Control3 = 0x09,
150 Mask1 = 0x0A,
151 Power = 0x0B,
152 Reset = 0x0C,
153 OcPreg = 0x0D,
154 MaskA = 0x0E,
155 MaskB = 0x0F,
156 Control4 = 0x10,
157 Status0A = 0x3C,
158 Status1A = 0x3D,
159 InterruptA = 0x3E,
160 InterruptB = 0x3F,
161 Status0 = 0x40,
162 Status1 = 0x41,
163 Interrupt = 0x42,
164 Fifo = 0x43,
165}
166
167bitfield! {
168 #[derive(Clone, Copy, PartialEq, Eq)]
169 pub struct DeviceId(pub u8): FromRaw, IntoRaw {
170 /// Device version ID by Trim or etc
171 pub version_id: u8 [read_only] @ 4..=7,
172 pub product_id: u8 [read_only] @ 2..=3,
173 /// Revision History of each version
174 pub revison_id: u8 [read_only] @ 0..=1,
175 }
176}
177
178impl Default for DeviceId {
179 fn default() -> Self {
180 Self(0b1001_0000)
181 }
182}
183
184bitfield! {
185 #[derive(Clone, Copy, PartialEq, Eq)]
186 pub struct Switches0(pub u8): FromRaw, IntoRaw {
187 /// Apply host pull up current to CC2 pin
188 pub pu_en2: bool @ 7,
189 /// Apply host pull up current to CC1 pin
190 pub pu_en1: bool @ 6,
191 /// Turn on the VCONN current to CC2 pin
192 pub vconn_cc2: bool @ 5,
193 /// Turn on the VCONN current to CC1 pin
194 pub vconn_cc1: bool @ 4,
195 /// Use the measure block to monitor or measure the voltage on CC2
196 pub meas_cc2: bool @ 3,
197 /// Use the measure block to monitor or measure the voltage on CC1
198 pub meas_cc1: bool @ 2,
199 /// Device pull down on CC2
200 pub pdwn2: bool @ 1,
201 /// Device pull down on CC1
202 pub pdwn1: bool @ 0,
203 }
204}
205
206impl Default for Switches0 {
207 fn default() -> Self {
208 Self(0b0000_0011)
209 }
210}
211
212/// Bit used for constructing the GoodCRC acknowledge packet
213#[derive(Clone, Copy)]
214pub enum Revision {
215 R1_0,
216 R2_0,
217}
218
219impl From<bool> for Revision {
220 fn from(value: bool) -> Self {
221 match value {
222 false => Self::R1_0,
223 true => Self::R2_0,
224 }
225 }
226}
227
228impl From<Revision> for bool {
229 fn from(revision: Revision) -> bool {
230 match revision {
231 Revision::R1_0 => false,
232 Revision::R2_0 => true,
233 }
234 }
235}
236
237bitfield! {
238 #[derive(Clone, Copy, PartialEq, Eq, Default)]
239 pub struct Switches1(pub u8): FromRaw, IntoRaw {
240 /// Bit used for constructing the GoodCRC acknowledge packet. This bit corresponds to the
241 /// Port Power Role bit in the message header if an SOP packet is received.
242 pub powerrole: bool [set PowerRole, get PowerRole] @ 7,
243 /// Bit used for constructing the GoodCRC acknowledge packet. These bits correspond to the
244 /// Specification Revision bits in the message header.
245 pub specrev: bool [set Revision, get Revision] @ 5,
246 /// Bit used for constructing the GoodCRC acknowledge packet. This bit corresponds to the
247 /// Port Data Role bit in the message header.
248 pub datarole: bool [set DataRole, get DataRole] @ 4,
249 /// Starts the transmitter automatically when a message with a good CRC is received and
250 /// automatically sends a GoodCRC acknowledge packet back to the relevant SOP*
251 pub auto_src: bool @ 2,
252 /// Enable BMC transmit driver on CC2 pin
253 pub txcc2: bool @ 1,
254 /// Enable BMC transmit driver on CC1 pin
255 pub txcc1: bool @ 0,
256 }
257}
258
259bitfield! {
260 #[derive(Clone, Copy, PartialEq, Eq, Default)]
261 pub struct Measure(pub u8): FromRaw, IntoRaw {
262 /// false: MDAC/comparator measurement is controlled by MEAS_CC* bits
263 /// true: Measure VBUS with the MDAC/comparator. This requires MEAS_CC* bits to be 0
264 pub meas_vbus: bool @ 6,
265 /// Measure Block DAC data input. LSB is equivalent to 42 mV of voltage which is compared
266 /// to the measured CC voltage. The measured CC is selected by MEAS_CC2, or MEAS_CC1 bits:
267 ///
268 /// | `MDAC[5:0]` | `MEAS_VBUS = 0` | `MEAS_VBUS = 1` | Unit |
269 /// |-------------|-----------------|-----------------|------|
270 /// | `00_0000` | 0.042 | 0.420 | V |
271 /// | `00_0001` | 0.084 | 0.840 | V |
272 /// | `11_0000` | 2.058 | 20.58 | V |
273 /// | `11_0011` | 2.184 | 21.84 | V |
274 /// | `11_1110` | 2.646 | 26.46 | V |
275 /// | `11_1111` | >2.688 | 26.88 | V |
276 /// | `11_1111` | >2.688 | 26.88 | V |
277 pub mdac: u8 @ 0..=5,
278 }
279}
280
281bitfield! {
282 #[derive(Clone, Copy, PartialEq, Eq, Default)]
283 pub struct Slice(pub u8): FromRaw, IntoRaw {
284 /// Adds hysteresis where there are now two thresholds, the lower threshold which is always
285 /// the value programmed by SDAC\[5:0\] and the higher threshold that is:
286 /// * `11`: 255 mV hysteresis: higher threshold = (SDAC value + 20hex)
287 /// * `10`: 170 mV hysteresis: higher threshold = (SDAC value + Ahex)
288 /// * `01`: 85 mV hysteresis: higher threshold = (SDAC value + 5)
289 /// * `00`: No hysteresis: higher threshold = SDAC value
290 pub sda_hys: u8 @ 6..=7,
291 /// BMC Slicer DAC data input. Allows for a programmable threshold so as to meet the BMC
292 /// receive mask under all noise conditions.
293 pub sdac: u8 @ 0..=5,
294 }
295}
296
297bitfield! {
298 #[derive(Clone, Copy, PartialEq, Eq, Default)]
299 pub struct Control0(pub u8): FromRaw, IntoRaw {
300 /// Self clearing bit to flush the content of the transmit FIFO
301 pub tx_flush: bool [write_only] @ 6,
302 /// Masks all interrupts, when false interrupts to host are enabled
303 pub int_mask: bool @ 5,
304 /// Controls the host pull up current enabled by PU_EN
305 ///
306 /// * `00`: No current
307 /// * `01`: 80 mA – Default USB power
308 /// * `10`: 180 mA – Medium Current Mode: 1.5 A
309 /// * `11`: 330 mA – High Current Mode: 3 A
310 pub host_cur: u8 @ 2..=3,
311
312 /// Starts the transmitter automatically when a message with a good CRC is received. This
313 /// allows the software to take as much as 300 mS to respond after the I_CRC_CHK interrupt
314 /// is received. Before starting the transmitter, an internal timer waits for approximately
315 /// 170 mS before executing the transmit start and preamble
316 pub auto_pre: bool @ 1,
317
318 /// Start transmitter using the data in the transmit FIFO. Preamble is started first.
319 /// During the preamble period the transmit data can start to be written to the transmit
320 /// FIFO. Self clearing.
321 pub tx_start: bool @ 0,
322 }
323}
324
325bitfield! {
326 #[derive(Clone, Copy, PartialEq, Eq, Default)]
327 pub struct Control1(pub u8): FromRaw, IntoRaw {
328 /// Enable SOP''_DEBUG (SOP double prime debug) packets, false for ignore
329 pub ensop2db: bool @ 6,
330 /// Enable SOP'_DEBUG (SOP prime debug) packets, false for ignore
331 pub ensop1db: bool @ 5,
332 /// Sent BIST Mode 01s pattern for testing
333 pub bist_mode2: bool @ 4,
334 /// Self clearing bit to flush the content of the receive FIFO
335 pub rx_flush: bool [write_only] @ 2,
336 /// Enable SOP'' (SOP double prime) packets, false for ignore
337 pub ensop2: bool @ 1,
338 /// Enable SOP' (SOP prime) packets, false for ignore
339 pub ensop1: bool @ 1,
340 }
341}
342
343bitfield! {
344 #[derive(Clone, Copy, PartialEq, Eq, Default)]
345 pub struct Control2(pub u8): FromRaw, IntoRaw {
346 /// * `00`: Don’t go into the DISABLE state after one cycle of toggle
347 /// * `01`: Wait between toggle cycles for tDIS time of 40 ms
348 /// * `10`: Wait between toggle cycles for tDIS time of 80 ms
349 /// * `11`: Wait between toggle cycles for tDIS time of 160 ms
350 pub tog_save_pwr: u8 @ 6..=7,
351
352 /// * `true`: When TOGGLE=1 only Rd values will cause the TOGGLE state machine to stop toggling and trigger the I_TOGGLE interrupt
353 /// * `false`: When TOGGLE=1, Rd and Ra values will cause the TOGGLE state machine to stop toggling
354 pub rog_rd_only: bool @ 5,
355
356 /// Enable Wake Detection functionality if the power state is correct
357 pub wake_end: bool @ 3,
358
359 /// * `11`: Enable SRC polling functionality if TOGGLE=1
360 /// * `10`: Enable SNK polling functionality if TOGGLE=1
361 /// * `01`: Enable DRP polling functionality if TOGGLE=1
362 /// * `00`: Do Not Use
363 pub mode: u8 @ 1..=2,
364
365 /// Enable DRP, SNK or SRC Toggle autonomous functionality
366 pub toggle: bool @ 0,
367 }
368}
369
370bitfield! {
371 #[derive(Clone, Copy, PartialEq, Eq, Default)]
372 pub struct Control3(pub u8): FromRaw, IntoRaw {
373 /// Send a hard reset packet (highest priority)
374 pub send_hard_reset: bool [write_only] @ 6,
375
376 /// BIST mode when enabled. Receive FIFO is cleared immediately after sending GoodCRC response.
377 ///
378 /// Normal operation when disabled; all packets are treated as usual.
379 pub bist_tmode: bool @ 5,
380
381 /// Enable automatic hard reset packet if soft reset fail
382 pub auto_hardreset: bool @ 4,
383
384 /// Enable automatic soft reset packet if retries fail
385 pub auto_softreset: bool @ 3,
386
387 /// * `11`: Three retries of packet (four total packets sent)
388 /// * `10`: Two retries of packet (three total packets sent)
389 /// * `01`: One retry of packet (two total packets sent)
390 /// * `00`: No retries (similar to disabling auto retry)
391 pub n_retries: u8 @ 1..=2,
392
393 /// Enable automatic packet retries if GoodCRC is not received
394 pub auto_retry: bool @ 0,
395 }
396}
397
398bitfield! {
399 #[derive(Clone, Copy, PartialEq, Eq, Default)]
400 pub struct Mask1(pub u8): FromRaw, IntoRaw {
401 /// Mask I_VBUSOK interrupt bit
402 pub m_vbusok: bool @ 7,
403 /// Mask interrupt for a transition in CC bus activity
404 pub m_activity: bool @ 6,
405 /// Mask I_COMP_CHNG interrupt for change is the value of COMP, the measure comparator
406 pub m_comp_chng: bool @ 5,
407 /// Mask interrupt from CRC_CHK bit
408 pub m_crc_chk: bool @ 4,
409 /// Mask the I_ALERT interrupt bit
410 pub m_alert: bool @ 3,
411 /// Mask the I_WAKE interrupt bit
412 pub m_wake: bool @ 2,
413 /// Mask the I_COLLISION interrupt bit
414 pub m_collision: bool @ 1,
415 /// Mask a change in host requested current level
416 pub m_bc_lvl: bool @ 0,
417 }
418}
419
420bitfield! {
421 #[derive(Clone, Copy, PartialEq, Eq, Format, Default)]
422 pub struct Power(pub u8): FromRaw, IntoRaw {
423 /// Enable internal oscillator
424 pub internal_oscillator: bool @ 3,
425 /// Measure block powered
426 pub measure_block: bool @ 2,
427 /// Receiver powered and current references for Measure block
428 pub receiver: bool @ 1,
429 /// Band gap and wake circuit
430 pub bandgap_wake: bool @ 0,
431 }
432}
433
434bitfield! {
435 #[derive(Clone, Copy, PartialEq, Eq, Default)]
436 pub struct Reset(pub u8): FromRaw, IntoRaw {
437 /// Reset just the PD logic for both the PD transmitter and receiver
438 pub pd_reset: bool @ 1,
439
440 /// Reset the FUSB302B including the I2C registers to their default values
441 pub sw_reset: bool @ 0,
442 }
443}
444
445bitfield! {
446 #[derive(Clone, Copy, PartialEq, Eq, Default)]
447 pub struct OcPreg(pub u8): FromRaw, IntoRaw {
448 /// * `true`: OCP range between 100−800 mA (max_range = 800 mA)
449 /// * `false`: OCP range between 10−80 mA (max_range = 80 mA)
450 pub ocp_range: bool @ 3,
451
452 /// * `111`: max_range (see bit definition above for OCP_RANGE)
453 /// * `110`: 7 * max_range / 8
454 /// * `101`: 6 * max_range / 8
455 /// * `100`: 5 * max_range / 8
456 /// * `011`: 4 * max_range / 8
457 /// * `010`: 3 * max_range / 8
458 /// * `001`: 2 * max_range / 8
459 /// * `000`: max_range / 8
460 pub ocp_cur: u8 @ 0..=2,
461 }
462}
463
464bitfield! {
465 #[derive(Clone, Copy, PartialEq, Eq, Default)]
466 pub struct MaskA(pub u8): FromRaw, IntoRaw {
467 /// Mask the I_OCP_TEMP interrupt
468 pub m_ocp_temp: bool @ 7,
469 /// Mask the I_TOGDONE interrupt
470 pub m_togdone: bool @ 6,
471 /// Mask the I_SOFTFAIL interrupt
472 pub m_softfail: bool @ 5,
473 /// Mask the I_RETRYFAIL interrupt
474 pub m_retryfail: bool @ 4,
475 /// Mask the I_HARDSENT interrupt
476 pub m_hardsent: bool @ 3,
477 /// Mask the I_TXSENT interrupt
478 pub m_txsent: bool @ 2,
479 /// Mask the I_SOFTRST interrupt
480 pub m_softrst: bool @ 1,
481 /// Mask the I_HARDRST interrupt
482 pub m_hardrst: bool @ 0,
483 }
484}
485
486bitfield! {
487 #[derive(Clone, Copy, PartialEq, Eq, Default)]
488 pub struct MaskB(pub u8): FromRaw, IntoRaw {
489 /// Mask the I_GCRCSENT interrupt
490 pub m_gcrcsent: bool @ 0,
491 }
492}
493
494bitfield! {
495 #[derive(Clone, Copy, PartialEq, Eq, Default)]
496 pub struct Control4(pub u8): FromRaw, IntoRaw {
497 /// In auto Rd only Toggle mode, stop Toggle at Audio accessory (Ra on both CC)
498 pub tog_exit_aud: bool @ 0,
499 }
500}
501
502bitfield! {
503 #[derive(Clone, Copy, PartialEq, Eq, Default)]
504 pub struct Status0A(pub u8): FromRaw, IntoRaw {
505 /// All soft reset packets with retries have failed to get a GoodCRC acknowledge. This
506 /// status is cleared when a START_TX, TXON or SEND_HARD_RESET is executed
507 pub softfail: bool [read_only] @ 5,
508
509 /// All packet retries have failed to get a GoodCRC acknowledge. This status is cleared
510 /// when a START_TX, TXON or SEND_HARD_RESET is executed
511 pub retryfail: bool [read_only] @ 4,
512
513 /// Internal power state when logic internals needs to control the power state. POWER3
514 /// corresponds to PWR3 bit and POWER2 corresponds to PWR2 bit. The power state is the
515 /// higher of both PWR\[3:0\] and {POWER3, POWER2, PWR\[1:0\]} so that if one is 03 and the
516 /// other is F then the internal power state is F.
517 pub power: u8 [read_only] @ 2..=3,
518
519 /// One of the packets received was a soft reset packet
520 pub softrst: bool [read_only] @ 1,
521
522 /// Hard Reset PD ordered set has been received
523 pub hardrst: bool [read_only] @ 0,
524 }
525}
526
527bitfield! {
528 #[derive(Clone, Copy, PartialEq, Eq, Default)]
529 pub struct Status1A(pub u8): FromRaw, IntoRaw {
530 /// * `000`: Toggle logic running (processor has previously written TOGGLE=1)
531 /// * `001`: Toggle functionality has settled to SRCon CC1 (STOP_SRC1 state)
532 /// * `010`: Toggle functionality has settled to SRCon CC2 (STOP_SRC2 state)
533 /// * `101`: Toggle functionality has settled to SNKon CC1 (STOP_SNK1 state)
534 /// * `110`: Toggle functionality has settled to SNKon CC2 (STOP_SNK2 state)
535 /// * `111`: Toggle functionality has detected AudioAccessory with vRa on both CC1 and CC2
536 /// (settles to STOP_SRC1 state)
537 ///
538 /// Otherwise: Not defined (do not interpret)
539 pub togss: u8 [read_only] @ 3..=5,
540
541 /// Indicates the last packet placed in the RxFIFO is type SOP''_DEBUG (SOP double prime
542 /// debug)
543 pub rxsop2db: bool [read_only] @ 2,
544
545 /// Indicates the last packet placed in the RxFIFO is type SOP'_DEBUG (SOP prime debug)
546 pub rxsop1db: bool [read_only] @ 1,
547
548 /// Indicates the last packet placed in the RxFIFO is type SOP
549 pub rxsop: bool [read_only] @ 0,
550 }
551}
552
553bitfield! {
554 #[derive(Clone, Copy, PartialEq, Eq, Default)]
555 pub struct InterruptA(pub u8): FromRaw, IntoRaw {
556 /// Interrupt from either a OCP event on one of the VCONN switches or an over-temperature
557 /// event
558 pub i_ocp_temp: bool @ 7,
559 /// Interrupt indicating the TOGGLE functionality was terminated because a device was
560 /// detected
561 pub i_togdone: bool @ 6,
562 /// Interrupt from automatic soft reset packets with retries have failed
563 pub i_softfail: bool @ 5,
564 /// Interrupt from automatic packet retries have failed
565 pub i_retryfail: bool @ 4,
566 /// Interrupt from successfully sending a hard reset ordered set
567 pub i_hardsent: bool @ 3,
568 /// Interrupt to alert that we sent a packet that was acknowledged with a GoodCRC response
569 /// packet
570 pub i_txsent: bool @ 2,
571 /// Received a soft reset packet
572 pub i_softrst: bool @ 1,
573 /// Received a hard reset ordered set
574 pub i_hardrst: bool @ 0,
575 }
576}
577
578bitfield! {
579 #[derive(Clone, Copy, PartialEq, Eq, Default)]
580 pub struct InterruptB(pub u8): FromRaw, IntoRaw {
581 /// Sent a GoodCRC acknowledge packet in response to an incoming packet that has the
582 /// correct CRC value
583 pub i_gcrcsent: bool @ 0,
584 }
585}
586
587bitfield! {
588 #[derive(Clone, Copy, PartialEq, Eq, Format, Default)]
589 pub struct Status0(pub u8): FromRaw, IntoRaw {
590 /// Interrupt occurs when VBUS transitions through vVBUSthr. This bit typically is used to
591 /// recognize port partner during startup
592 pub vbusok: bool [read_only] @ 7,
593
594 /// Transitions are detected on the active CC* line. This bit goes high after a minimum of
595 /// 3 CC transitions, and goes low with no Transitions
596 pub activity: bool [read_only] @ 6,
597
598 /// Measured CC* input is higher than reference level driven from the MDAC
599 pub comp: bool [read_only] @ 5,
600
601 /// Indicates the last received packet had the correct CRC. This bit remains set until the
602 /// SOP of the next packet
603 ///
604 /// If false, packet received for an enabled SOP* and CRC for the enabled packet received
605 /// was incorrect
606 pub crc_chk: bool [read_only] @ 4,
607
608 /// Alert software an error condition has occurred. An alert is caused by:
609 /// * TX_FULL: the transmit FIFO is full
610 /// * RX_FULL: the receive FIFO is full
611 ///
612 /// See Status1 bits
613 pub alert: bool [read_only] @ 3,
614
615 /// * `true`: Voltage on CC indicated a device attempting to attach
616 /// * `false`: WAKE either not enabled (WAKE_EN=0) or no device attached
617 pub wake: bool [read_only] @ 2,
618
619 /// Current voltage status of the measured CC pin interpreted as host current levels as
620 /// follows:
621 ///
622 /// * `00`: < 200 mV
623 /// * `01`: > 200mV, < 660mV
624 /// * `10`: > 660mV, < 1.23V
625 /// * `11`: > 1.23 V
626 ///
627 /// Note the software must measure these at an appropriate time, while there is no signaling
628 /// activity on the selected CC line. BC_LVL is only defined when Measure block is on which
629 /// is when register bits PWR\[2\]=1 and either MEAS_CC1=1 or MEAS_CC2=1
630 pub bc_lvl: u8 [read_only] @ 0..=1,
631 }
632}
633
634bitfield! {
635 #[derive(Clone, Copy, PartialEq, Eq, Format, Default)]
636 pub struct Status1(pub u8): FromRaw, IntoRaw {
637 /// Indicates the last packet placed in the RxFIFO is type SOP'' (SOP double prime)
638 pub rxsop2: bool [read_only] @ 7,
639 /// Indicates the last packet placed in the RxFIFO is type SOP' (SOP prime)
640 pub rxsop1: bool [read_only] @ 6,
641 /// The receive FIFO is empty
642 pub rx_empty: bool [read_only] @ 5,
643 /// The receive FIFO is full
644 pub rx_full: bool [read_only] @ 4,
645 /// The transmit FIFO is empty
646 pub tx_empty: bool [read_only] @ 3,
647 /// The transmit FIFO is full
648 pub tx_full: bool [read_only] @ 2,
649 /// Temperature of the device is too high
650 pub overtemp: bool [read_only] @ 1,
651 /// Indicates an over-current or short condition has occurred on the VCONN switch
652 pub ocp: bool [read_only] @ 0,
653 }
654}
655
656bitfield! {
657 #[derive(Clone, Copy, PartialEq, Eq, Default)]
658 pub struct Interrupt(pub u8): FromRaw, IntoRaw {
659 /// Interrupt occurs when VBUS transitions through 4.5 V. This bit typically is used to recognize port partner during startup
660 pub i_vbusok: bool @ 7,
661
662 /// A change in the value of ACTIVITY of the CC bus has oc- curred
663 pub i_activity: bool @ 6,
664
665 /// A change in the value of COMP has occurred. Indicates se- lected CC line has tripped a threshold programmed into the MDAC
666 pub i_comp_chng: bool @ 5,
667
668 /// The value of CRC_CHK newly valid. I.e. The validity of the incoming packet has been checked
669 pub i_crc_chk: bool @ 4,
670
671 /// Alert software an error condition has occurred. An alert is caused by:
672 ///
673 /// * TX_FULL: the transmit FIFO is full
674 /// * RX_FULL: the receive FIFO is full See Status1 bits
675 pub i_alert: bool @ 3,
676
677 /// Voltage on CC indicated a device attempting to attach. Software must then power up the clock and receiver blocks
678 pub i_wake: bool @ 2,
679
680 /// When a transmit was attempted, activity was detected on the active CC line. Transmit is not done. The packet is received normally
681 pub i_collision: bool @ 1,
682
683 /// A change in host requested current level has occurred
684 pub i_bc_lvl: bool @ 0,
685 }
686}
687
688bitfield! {
689 #[derive(Clone, Copy, PartialEq, Eq, Default)]
690 pub struct Fifo(pub u8): FromRaw, IntoRaw {
691 /// Writing to this register writes a byte into the transmit FIFO. Reading from this register reads from the receive FIFO.
692 /// Each byte is a coded token. Or a token followed by a fixed number of packed data byte (see token coding in Table 41)
693 pub token: u8 @ 0..7,
694 }
695}