fst_writer/
types.rs

1// Copyright 2024 Cornell University
2// released under BSD 3-Clause License
3// author: Kevin Laeufer <laeufer@cornell.edu>
4
5use std::num::NonZeroU32;
6
7#[repr(u8)]
8#[derive(Debug, Clone, Copy, PartialEq)]
9pub enum FstFileType {
10    Verilog = 0,
11    Vhdl = 1,
12    VerilogVhdl = 2,
13}
14
15#[derive(Debug, Clone)]
16pub struct FstInfo {
17    pub start_time: u64,
18    // TODO: better abstraction
19    /// All times in the file are stored in units of 10^timescale_exponent s.
20    pub timescale_exponent: i8,
21    pub version: String,
22    pub date: String,
23    pub file_type: FstFileType,
24}
25
26#[derive(Debug, Copy, Clone, Ord, PartialOrd, Eq, PartialEq, Hash)]
27pub struct FstSignalId(NonZeroU32);
28
29impl FstSignalId {
30    pub(crate) fn from_index(index: u32) -> Self {
31        FstSignalId(NonZeroU32::new(index).unwrap())
32    }
33
34    /// The raw value used in the FST file format.
35    pub(crate) fn to_index(self) -> u32 {
36        self.0.get()
37    }
38
39    pub(crate) fn to_array_index(self) -> usize {
40        self.0.get() as usize - 1
41    }
42}
43
44#[derive(Debug, Copy, Clone, PartialEq)]
45pub struct FstSignalType(SignalType);
46
47#[derive(Debug, Copy, Clone, PartialEq)]
48enum SignalType {
49    BitVec(NonZeroU32),
50    Real,
51}
52
53impl FstSignalType {
54    pub fn bit_vec(len: u32) -> Self {
55        Self(SignalType::BitVec(NonZeroU32::new(len + 1).unwrap()))
56    }
57
58    pub fn real() -> Self {
59        Self(SignalType::Real)
60    }
61
62    pub(crate) fn to_file_format(self) -> u32 {
63        match self.0 {
64            SignalType::BitVec(value) => match value.get() {
65                1 => u32::MAX,
66                other => other - 1,
67            },
68            SignalType::Real => 0,
69        }
70    }
71
72    #[inline]
73    pub(crate) fn len(&self) -> u32 {
74        match self.0 {
75            SignalType::BitVec(value) => value.get() - 1,
76            SignalType::Real => 8,
77        }
78    }
79}
80
81#[repr(u8)]
82#[derive(Debug, Clone, Copy, PartialEq)]
83pub enum FstScopeType {
84    // VCD
85    Module = 0,
86    Task = 1,
87    Function = 2,
88    Begin = 3,
89    Fork = 4,
90    Generate = 5,
91    Struct = 6,
92    Union = 7,
93    Class = 8,
94    Interface = 9,
95    Package = 10,
96    Program = 11,
97    // VHDL
98    VhdlArchitecture = 12,
99    VhdlProcedure = 13,
100    VhdlFunction = 14,
101    VhdlRecord = 15,
102    VhdlProcess = 16,
103    VhdlBlock = 17,
104    VhdlForGenerate = 18,
105    VhdlIfGenerate = 19,
106    VhdlGenerate = 20,
107    VhdlPackage = 21,
108}
109
110#[repr(u8)]
111#[derive(Debug, PartialEq, Copy, Clone)]
112pub enum FstVarType {
113    // VCD
114    Event = 0,
115    Integer = 1,
116    Parameter = 2,
117    Real = 3,
118    RealParameter = 4,
119    Reg = 5,
120    Supply0 = 6,
121    Supply1 = 7,
122    Time = 8,
123    Tri = 9,
124    TriAnd = 10,
125    TriOr = 11,
126    TriReg = 12,
127    Tri0 = 13,
128    Tri1 = 14,
129    Wand = 15, // or WAnd ?
130    Wire = 16,
131    Wor = 17, // or WOr?
132    Port = 18,
133    SparseArray = 19,
134    RealTime = 20,
135    GenericString = 21,
136    // System Verilog
137    Bit = 22,
138    Logic = 23,
139    Int = 24,
140    ShortInt = 25,
141    LongInt = 26,
142    Byte = 27,
143    Enum = 28,
144    ShortReal = 29,
145}
146
147#[repr(u8)]
148#[derive(Debug, Clone, Copy, PartialEq)]
149pub enum FstVarDirection {
150    Implicit = 0,
151    Input = 1,
152    Output = 2,
153    InOut = 3,
154    Buffer = 4,
155    Linkage = 5,
156}
fst_writer/types.rs

fst_writer/
types.rs
