Struct flipper0::ffi::LL_ADC_REG_InitTypeDef

pub struct LL_ADC_REG_InitTypeDef {
    pub TriggerSource: u32,
    pub SequencerLength: u32,
    pub SequencerDiscont: u32,
    pub ContinuousMode: u32,
    pub DMATransfer: u32,
    pub Overrun: u32,
}

@brief Structure definition of some features of ADC group regular. @note These parameters have an impact on ADC scope: ADC group regular. Refer to corresponding unitary functions into @ref ADC_LL_EF_Configuration_ADC_Group_Regular (functions with prefix “REG”). @note The setting of these parameters by function @ref LL_ADC_REG_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, …) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.

Fields

TriggerSource: u32

< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line). This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().

This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource().

SequencerLength: u32

< Set ADC group regular sequencer length. This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH

This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength().

SequencerDiscont: u32

< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE @note This parameter has an effect only if group regular sequencer is enabled (scan length of 2 ranks or more).

This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont().

ContinuousMode: u32

< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.

This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode().

DMATransfer: u32

< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER

This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer().

Overrun: u32

< Set ADC group regular behavior in case of overrun: data preserved or overwritten. This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR

This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun().

Trait Implementations

impl Debug for LL_ADC_REG_InitTypeDef

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.