1mod expr;
2mod string;
3mod types;
4
5pub type IDStr = String;
8
9pub type Info = String;
11
12#[derive(Debug, Clone)]
13pub struct Circuit {
14 id: IDStr,
15 infos: Vec<Info>,
16 modules: Vec<Module>,
17}
18
19#[derive(Debug, Clone)]
20pub struct Module {
21 id: IDStr,
22 infos: Vec<Info>,
23 ports: Vec<Port>,
24 stmt: Stmt,
25}
26
27#[derive(Debug, Clone)]
28pub struct Port {
29 direction: Direction,
30 id: IDStr,
31 ty: Type,
32 infos: Vec<Info>,
33}
34
35#[derive(Debug, Clone)]
36pub enum Direction {
37 I,
38 O,
39}
40
41#[derive(Debug, Clone)]
42pub enum Type {
43 UInt {
44 width: Option<usize>,
45 },
46 SInt {
47 width: Option<usize>,
48 },
49 Fixed {
50 width: Option<usize>,
51 point: Option<usize>,
52 },
53 Clock,
54 Analog {
55 width: Option<usize>,
56 },
57 Bundle {
58 fields: Vec<Field>,
59 },
60 Vector {
61 ty: Box<Type>,
62 len: usize,
63 },
64}
65
66#[derive(Debug, Clone)]
67pub enum Field {
68 Flipped(FieldInner),
69 Default(FieldInner),
70}
71
72#[derive(Debug, Clone)]
73pub struct FieldInner {
74 id: IDStr,
75 ty: Type,
76 infos: Vec<Info>,
77}
78
79#[derive(Debug, Clone)]
80pub enum Stmt {
81 Wire(Wire),
82 Reg(Reg),
83 Mem(Mem),
84 Instance(Instance),
85 Node(Node),
86 Connect(Connect),
87 PartialConnect(Connect),
88 Invalidate(Invalidate),
89 Attatch(Attatch),
90 Conditional(Conditional),
91 Stop(Stop),
92 Printf(Printf),
93 Empty(Empty),
94 Group(Vec<Stmt>),
95}
96
97#[derive(Debug, Clone)]
98pub struct Wire {
99 id: IDStr,
100 ty: Type,
101 infos: Vec<Info>,
102}
103
104#[derive(Debug, Clone)]
105pub struct Reg {
106 id: IDStr,
107 ty: Type,
108 clk: IDStr,
109 init: RegInit,
110 infos: Vec<Info>,
111}
112
113#[derive(Debug, Clone)]
114pub struct RegInit {
115 signal: Expr,
116 val: Expr,
117}
118
119#[derive(Debug, Clone)]
120pub struct Mem {
121 id: IDStr,
122 infos: Vec<Info>,
123 opts: MemOpts,
124}
125
126#[derive(Debug, Clone)]
127pub struct MemOpts {
128 data_type: Type,
129 depth: usize,
130 read_latency: usize,
131 write_latency: usize,
132 read_under_write: ReadUnderWrite,
133 r_ports: Vec<IDStr>,
134 w_ports: Vec<IDStr>,
135 rw_ports: Vec<IDStr>,
136}
137
138#[derive(Debug, Clone)]
139pub enum ReadUnderWrite {
140 Old,
141 New,
142 Undefined,
143}
144
145#[derive(Debug, Clone)]
146pub struct Instance {
147 id: String,
148 infos: Vec<Info>,
149}
150
151#[derive(Debug, Clone)]
152pub struct Node {
153 id: String,
154 rhs: Expr,
155 infos: Vec<Info>,
156}
157
158#[derive(Debug, Clone)]
159pub struct Connect {
160 lhs: Expr,
161 rhs: Expr,
162 infos: Vec<Info>,
163}
164
165#[derive(Debug, Clone)]
166pub struct Invalidate {
167 lhs: Expr,
168 infos: Vec<Info>,
169}
170
171#[derive(Debug, Clone)]
172pub struct Attatch {
173 exprs: Expr,
174 infos: Vec<Info>,
175}
176
177#[derive(Debug, Clone)]
178pub struct Conditional {
179 cond: Expr,
180 infos: Vec<Info>,
181 if_true: Box<Stmt>,
182 if_false: Box<Stmt>,
183}
184
185#[derive(Debug, Clone)]
186pub struct Stop {
187 clk: Expr,
188 halt: Expr,
189 exit_code: i32,
190 id: Option<IDStr>,
191 infos: Vec<Info>,
192}
193
194#[derive(Debug, Clone)]
195pub struct Printf {
196 clk: Expr,
197 print_signal: Expr,
198 fmt: String,
199 params: Vec<Expr>,
200}
201
202#[derive(Debug, Clone)]
203pub struct Empty {
204 infos: Vec<Info>,
205}
206
207#[derive(Debug, Clone)]
208pub enum Expr {
209 Literal(Literal),
210 Ref(IDStr),
211 Field(Box<Expr>, IDStr),
212 Access(Box<Expr>, usize),
213 DynAccess(Box<Expr>, Box<Expr>),
214 Mux(Box<Expr>, Box<Expr>, Box<Expr>),
215 CondValid(Box<Expr>, Box<Expr>),
216 PrimOp(PrimOpExpr),
217}
218
219#[derive(Debug, Clone)]
220pub enum Literal {
221 UInt(LitVal, Option<usize>),
222 SInt(LitVal, Option<usize>),
223}
224
225#[derive(Debug, Clone)]
226pub enum LitVal {
227 Hex(String),
228 Oct(String),
229 Bin(String),
230 Dec(String),
231}
232
233#[derive(Debug, Clone)]
234pub enum PrimOpExpr {
235 Add(Box<Expr>, Box<Expr>),
236 Sub(Box<Expr>, Box<Expr>),
237 Mul(Box<Expr>, Box<Expr>),
238 Div(Box<Expr>, Box<Expr>),
239 Mod(Box<Expr>, Box<Expr>),
240 Lt(Box<Expr>, Box<Expr>),
241 Leq(Box<Expr>, Box<Expr>),
242 Gt(Box<Expr>, Box<Expr>),
243 Geq(Box<Expr>, Box<Expr>),
244 Eq(Box<Expr>, Box<Expr>),
245 Neq(Box<Expr>, Box<Expr>),
246 Pad(Box<Expr>, usize),
247 AsUInt(Box<Expr>),
248 AsSInt(Box<Expr>),
249 AsFixed(Box<Expr>),
250 AsClock(Box<Expr>),
251 Shl(Box<Expr>, usize),
252 Shr(Box<Expr>, usize),
253 DynShl(Box<Expr>, Box<Expr>),
254 DynShr(Box<Expr>, Box<Expr>),
255 ArithCvtSigned(Box<Expr>),
256 Neg(Box<Expr>),
257 Not(Box<Expr>),
258 And(Box<Expr>, Box<Expr>),
259 Or(Box<Expr>, Box<Expr>),
260 Xor(Box<Expr>, Box<Expr>),
261 Andr(Box<Expr>),
262 Orr(Box<Expr>),
263 Xorr(Box<Expr>),
264 Concat(Box<Expr>, Box<Expr>),
265 Bits(Box<Expr>, usize, usize),
266 Head(Box<Expr>, usize),
267 Tail(Box<Expr>, usize),
268 IncP(Box<Expr>, usize),
269 DecP(Box<Expr>, usize),
270 SetP(Box<Expr>, usize),
271}
272
273#[derive(Debug, Copy, Clone)]
274pub enum PrimOp {
275 Add,
276 Sub,
277 Mul,
278 Div,
279 Mod,
280 Lt,
281 Leq,
282 Gt,
283 Geq,
284 Eq,
285 Neq,
286 Pad,
287 AsUInt,
288 AsSInt,
289 AsClock,
290 AsFixed,
291 Shl,
292 Shr,
293 DynShl,
294 DynShr,
295 ArithCvtSigned,
296 Neg,
297 Not,
298 And,
299 Or,
300 Xor,
301 Andr,
302 Orr,
303 Xorr,
304 Concat,
305 Bits,
306 Head,
307 Tail,
308 IncP,
309 DecP,
310 SetP,
311}
312
313#[cfg(test)]
314mod tests {
315 #[test]
316 fn it_works() {
317 assert_eq!(2 + 2, 4);
318 }
319}