fidget_core/compiler/
mod.rs

1//! Compiler infrastructure
2//!
3//! The Fidget compiler operates in several stages:
4//! - A math graph (specified as a [`Context`](crate::Context) and
5//!   [`Node`](crate::context::Node)) is flattened into an [`SsaTape`], i.e. a
6//!   set of operations in single-static assignment form.
7//! - The [`SsaTape`] goes through [register allocation](RegisterAllocator) and
8//!   becomes a [`RegTape`], planned with some number of registers.
9
10mod alloc;
11pub use alloc::RegisterAllocator;
12
13mod op;
14
15mod lru;
16pub(crate) use lru::Lru;
17pub use op::{RegOp, SsaOp};
18
19mod reg_tape;
20mod ssa_tape;
21
22pub use reg_tape::RegTape;
23pub use ssa_tape::SsaTape;
24
25#[cfg(test)]
26mod test {
27    use super::*;
28    #[test]
29    fn test_vm_op_size() {
30        assert_eq!(std::mem::size_of::<RegOp>(), 8);
31        assert_eq!(std::mem::size_of::<SsaOp>(), 16);
32    }
33}