Crate ferric_tensor 

Ferric L2 — a general N-dimensional tensor runtime on the GPU fabric.

This is the substrate the whole ecosystem is meant to stand on: not fixed-shape, hand-fused kernels for one architecture, but a real tensor with arbitrary rank, strided views, and broadcasting, plus general elementwise ops, general reductions over any axes, and batched matmul. The transformer kernels in ferric-core become fused fast-paths of this.

Design: eager execution, tensors are Arc-shared f32 buffers described by (shape, strides, offset). Views (reshape/permute/transpose/broadcast_to) are zero-copy stride tricks; contiguous() materializes. One general strided kernel powers elementwise + broadcasting; a segmented kernel powers reductions; a batched kernel powers matmul. Validated against a strided CPU reference on general shapes (broadcasting, non-contiguous inputs, arbitrary reduction axes).

Next fabric layers (in progress): dtypes (f16/bf16/int), autograd tape for training, op fusion, and the heterogeneous scheduler.

Re-exports

pub use autograd::Var;

pub use dtype::DType;

pub use dtype::Half;

pub use dtype::QRow;

pub use dtype::QTensor;

pub use dtype::Ternary;

pub use optim::Adam;

Modules

autograd

Reverse-mode automatic differentiation over the general tensor runtime — the layer that turns Ferric from an inference demo into a fabric that can train. A Var wraps a Tensor and records how to backpropagate through each op; backward() walks the graph in reverse and accumulates gradients (broadcasting-aware). Params live as plain Tensors and are re-wrapped each step, so an optimizer is just tensor arithmetic.

cpu

Plain-Rust reference on logical (row-major) data — the source of truth for the GPU tensor runtime. Operates on the same logical layout Tensor::to_vec returns, so comparisons are apples-to-apples.

dtype

Precision / storage dtypes for the fabric. Compute stays f32 (WebGPU-baseline has no shader-f16), but weights can LIVE on the GPU in half precision and be dequantized on-device — half the memory, and the path real fp16/bf16 checkpoints take. Half is a packed storage tensor (2 values per u32 word); dequant() expands to a compute Tensor, Tensor::to_half() packs one down.

fuse

Kernel fusion via runtime WGSL codegen — the seed of Ferric’s optimizing compiler. An elementwise expression over input tensors is compiled to ONE WGSL kernel and dispatched once: no per-op intermediate buffers, no per-op dispatch/readback. E::input(0).silu().mul(&E::input(1)) (a SwiGLU gate) becomes a single kernel instead of two ops + a temp. SSA codegen with common-subexpression sharing (each DAG node emitted once). This is what closes the perf gap with hand-fused C++/CUDA.

nn

Transformer building blocks expressed ON the general tensor runtime. The point of unification: attention is not a bespoke kernel — it’s reshape → batched matmul → softmax → matmul, i.e. the general ops. RMSNorm/softmax/RoPE are fused fast-paths (methods on Tensor) but produce exactly what composing primitives would. One substrate; the model is an expression in it.

optim

Optimizers — plain tensor arithmetic over the general runtime. Adam keeps per-parameter first/ second moment estimates and applies bias-corrected updates entirely on the GPU.

sched

L7 — the heterogeneous scheduler. Presents whatever compute is present as one fabric and partitions work across it. Here the devices are a GPU (wgpu) and the CPU (plain Rust) — two genuinely different fabrics on any machine. Data crosses device boundaries as host buffers, which is exactly the format that would serialize to a cloud node or postMessage to a browser worker, so the same Device/Fabric abstraction extends to cloud+local+browser.

ws

A tiny dependency-free WebSocket bridge so the scheduler can reach a browser tab as a device. Browsers can’t accept raw TCP, but a tab connects out via WebSocket — so we run a small HTTP server that serves the worker page + wasm and upgrades /ws to a WebSocket. Op frames (the same host-buffer format as Device::Remote) ride the socket to the tab, which computes on WebGPU and sends the result back. RFC 6455 handshake (SHA-1 + base64) and frame codec implemented inline.

Structs

Tensor

A general N-D f32 tensor: an Arc-shared device buffer viewed through (shape, strides, offset).