[]Struct feather_f405::pac::otg_hs_device::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub dcfg: Reg<u32, _DCFG>,
    pub dctl: Reg<u32, _DCTL>,
    pub dsts: Reg<u32, _DSTS>,
    pub diepmsk: Reg<u32, _DIEPMSK>,
    pub doepmsk: Reg<u32, _DOEPMSK>,
    pub daint: Reg<u32, _DAINT>,
    pub daintmsk: Reg<u32, _DAINTMSK>,
    pub dvbusdis: Reg<u32, _DVBUSDIS>,
    pub dvbuspulse: Reg<u32, _DVBUSPULSE>,
    pub dthrctl: Reg<u32, _DTHRCTL>,
    pub diepempmsk: Reg<u32, _DIEPEMPMSK>,
    pub deachint: Reg<u32, _DEACHINT>,
    pub deachintmsk: Reg<u32, _DEACHINTMSK>,
    pub diepeachmsk1: Reg<u32, _DIEPEACHMSK1>,
    pub doepeachmsk1: Reg<u32, _DOEPEACHMSK1>,
    pub diepctl0: Reg<u32, _DIEPCTL0>,
    pub diepint0: Reg<u32, _DIEPINT>,
    pub dieptsiz0: Reg<u32, _DIEPTSIZ0>,
    pub diepdma1: Reg<u32, _DIEPDMA1>,
    pub dtxfsts0: Reg<u32, _DTXFSTS>,
    pub diepctl1: Reg<u32, _DIEPCTL>,
    pub diepint1: Reg<u32, _DIEPINT>,
    pub dieptsiz1: Reg<u32, _DIEPTSIZ>,
    pub diepdma2: Reg<u32, _DIEPDMA2>,
    pub dtxfsts1: Reg<u32, _DTXFSTS>,
    pub diepctl2: Reg<u32, _DIEPCTL>,
    pub diepint2: Reg<u32, _DIEPINT>,
    pub dieptsiz2: Reg<u32, _DIEPTSIZ>,
    pub diepdma3: Reg<u32, _DIEPDMA3>,
    pub dtxfsts2: Reg<u32, _DTXFSTS>,
    pub diepctl3: Reg<u32, _DIEPCTL>,
    pub diepint3: Reg<u32, _DIEPINT>,
    pub dieptsiz3: Reg<u32, _DIEPTSIZ>,
    pub diepdma4: Reg<u32, _DIEPDMA4>,
    pub dtxfsts3: Reg<u32, _DTXFSTS>,
    pub diepctl4: Reg<u32, _DIEPCTL>,
    pub diepint4: Reg<u32, _DIEPINT>,
    pub dieptsiz4: Reg<u32, _DIEPTSIZ>,
    pub diepdma5: Reg<u32, _DIEPDMA5>,
    pub dtxfsts4: Reg<u32, _DTXFSTS>,
    pub diepctl5: Reg<u32, _DIEPCTL>,
    pub diepint5: Reg<u32, _DIEPINT>,
    pub dieptsiz5: Reg<u32, _DIEPTSIZ>,
    pub dtxfsts5: Reg<u32, _DTXFSTS>,
    pub doepctl0: Reg<u32, _DOEPCTL0>,
    pub doepint0: Reg<u32, _DOEPINT>,
    pub doeptsiz0: Reg<u32, _DOEPTSIZ0>,
    pub doepctl1: Reg<u32, _DOEPCTL>,
    pub doepint1: Reg<u32, _DOEPINT>,
    pub doeptsiz1: Reg<u32, _DOEPTSIZ>,
    pub doepctl2: Reg<u32, _DOEPCTL>,
    pub doepint2: Reg<u32, _DOEPINT>,
    pub doeptsiz2: Reg<u32, _DOEPTSIZ>,
    pub doepctl3: Reg<u32, _DOEPCTL>,
    pub doepint3: Reg<u32, _DOEPINT>,
    pub doeptsiz3: Reg<u32, _DOEPTSIZ>,
    pub doepctl4: Reg<u32, _DOEPCTL>,
    pub doepint4: Reg<u32, _DOEPINT>,
    pub doeptsiz4: Reg<u32, _DOEPTSIZ>,
    pub doepctl5: Reg<u32, _DOEPCTL>,
    pub doepint5: Reg<u32, _DOEPINT>,
    pub doeptsiz5: Reg<u32, _DOEPTSIZ>,
    // some fields omitted
}

Register block

Fields

dcfg: Reg<u32, _DCFG>

0x00 - OTG_HS device configuration register

dctl: Reg<u32, _DCTL>

0x04 - OTG_HS device control register

dsts: Reg<u32, _DSTS>

0x08 - OTG_HS device status register

diepmsk: Reg<u32, _DIEPMSK>

0x10 - OTG_HS device IN endpoint common interrupt mask register

doepmsk: Reg<u32, _DOEPMSK>

0x14 - OTG_HS device OUT endpoint common interrupt mask register

daint: Reg<u32, _DAINT>

0x18 - OTG_HS device all endpoints interrupt register

daintmsk: Reg<u32, _DAINTMSK>

0x1c - OTG_HS all endpoints interrupt mask register

dvbusdis: Reg<u32, _DVBUSDIS>

0x28 - OTG_HS device VBUS discharge time register

dvbuspulse: Reg<u32, _DVBUSPULSE>

0x2c - OTG_HS device VBUS pulsing time register

dthrctl: Reg<u32, _DTHRCTL>

0x30 - OTG_HS Device threshold control register

diepempmsk: Reg<u32, _DIEPEMPMSK>

0x34 - OTG_HS device IN endpoint FIFO empty interrupt mask register

deachint: Reg<u32, _DEACHINT>

0x38 - OTG_HS device each endpoint interrupt register

deachintmsk: Reg<u32, _DEACHINTMSK>

0x3c - OTG_HS device each endpoint interrupt register mask

diepeachmsk1: Reg<u32, _DIEPEACHMSK1>

0x40 - OTG_HS device each in endpoint-1 interrupt register

doepeachmsk1: Reg<u32, _DOEPEACHMSK1>

0x80 - OTG_HS device each OUT endpoint-1 interrupt register

diepctl0: Reg<u32, _DIEPCTL0>

0x100 - OTG device endpoint-0 control register

diepint0: Reg<u32, _DIEPINT>

0x108 - OTG device endpoint-0 interrupt register

dieptsiz0: Reg<u32, _DIEPTSIZ0>

0x110 - OTG_HS device IN endpoint 0 transfer size register

diepdma1: Reg<u32, _DIEPDMA1>

0x114 - OTG_HS device endpoint-1 DMA address register

dtxfsts0: Reg<u32, _DTXFSTS>

0x118 - OTG_HS device IN endpoint transmit FIFO status register

diepctl1: Reg<u32, _DIEPCTL>

0x120 - OTG device endpoint-1 control register

diepint1: Reg<u32, _DIEPINT>

0x128 - OTG device endpoint-0 interrupt register

dieptsiz1: Reg<u32, _DIEPTSIZ>

0x130 - OTG_HS device endpoint transfer size register

diepdma2: Reg<u32, _DIEPDMA2>

0x134 - OTG_HS device endpoint-2 DMA address register

dtxfsts1: Reg<u32, _DTXFSTS>

0x138 - OTG_HS device IN endpoint transmit FIFO status register

diepctl2: Reg<u32, _DIEPCTL>

0x140 - OTG device endpoint-1 control register

diepint2: Reg<u32, _DIEPINT>

0x148 - OTG device endpoint-0 interrupt register

dieptsiz2: Reg<u32, _DIEPTSIZ>

0x150 - OTG_HS device endpoint transfer size register

diepdma3: Reg<u32, _DIEPDMA3>

0x154 - OTG_HS device endpoint-3 DMA address register

dtxfsts2: Reg<u32, _DTXFSTS>

0x158 - OTG_HS device IN endpoint transmit FIFO status register

diepctl3: Reg<u32, _DIEPCTL>

0x160 - OTG device endpoint-1 control register

diepint3: Reg<u32, _DIEPINT>

0x168 - OTG device endpoint-0 interrupt register

dieptsiz3: Reg<u32, _DIEPTSIZ>

0x170 - OTG_HS device endpoint transfer size register

diepdma4: Reg<u32, _DIEPDMA4>

0x174 - OTG_HS device endpoint-4 DMA address register

dtxfsts3: Reg<u32, _DTXFSTS>

0x178 - OTG_HS device IN endpoint transmit FIFO status register

diepctl4: Reg<u32, _DIEPCTL>

0x180 - OTG device endpoint-1 control register

diepint4: Reg<u32, _DIEPINT>

0x188 - OTG device endpoint-0 interrupt register

dieptsiz4: Reg<u32, _DIEPTSIZ>

0x190 - OTG_HS device endpoint transfer size register

diepdma5: Reg<u32, _DIEPDMA5>

0x194 - OTG_HS device endpoint-5 DMA address register

dtxfsts4: Reg<u32, _DTXFSTS>

0x198 - OTG_HS device IN endpoint transmit FIFO status register

diepctl5: Reg<u32, _DIEPCTL>

0x1a0 - OTG device endpoint-1 control register

diepint5: Reg<u32, _DIEPINT>

0x1a8 - OTG device endpoint-0 interrupt register

dieptsiz5: Reg<u32, _DIEPTSIZ>

0x1b0 - OTG_HS device endpoint transfer size register

dtxfsts5: Reg<u32, _DTXFSTS>

0x1b8 - OTG_HS device IN endpoint transmit FIFO status register

doepctl0: Reg<u32, _DOEPCTL0>

0x300 - OTG_HS device control OUT endpoint 0 control register

doepint0: Reg<u32, _DOEPINT>

0x308 - OTG_HS device endpoint-0 interrupt register

doeptsiz0: Reg<u32, _DOEPTSIZ0>

0x310 - OTG_HS device endpoint-1 transfer size register

doepctl1: Reg<u32, _DOEPCTL>

0x320 - OTG device endpoint-1 control register

doepint1: Reg<u32, _DOEPINT>

0x328 - OTG_HS device endpoint-0 interrupt register

doeptsiz1: Reg<u32, _DOEPTSIZ>

0x330 - OTG_HS device endpoint-2 transfer size register

doepctl2: Reg<u32, _DOEPCTL>

0x340 - OTG device endpoint-1 control register

doepint2: Reg<u32, _DOEPINT>

0x348 - OTG_HS device endpoint-0 interrupt register

doeptsiz2: Reg<u32, _DOEPTSIZ>

0x350 - OTG_HS device endpoint-2 transfer size register

doepctl3: Reg<u32, _DOEPCTL>

0x360 - OTG device endpoint-1 control register

doepint3: Reg<u32, _DOEPINT>

0x368 - OTG_HS device endpoint-0 interrupt register

doeptsiz3: Reg<u32, _DOEPTSIZ>

0x370 - OTG_HS device endpoint-2 transfer size register

doepctl4: Reg<u32, _DOEPCTL>

0x380 - OTG device endpoint-1 control register

doepint4: Reg<u32, _DOEPINT>

0x388 - OTG_HS device endpoint-0 interrupt register

doeptsiz4: Reg<u32, _DOEPTSIZ>

0x390 - OTG_HS device endpoint-2 transfer size register

doepctl5: Reg<u32, _DOEPCTL>

0x3a0 - OTG device endpoint-1 control register

doepint5: Reg<u32, _DOEPINT>

0x3a8 - OTG_HS device endpoint-0 interrupt register

doeptsiz5: Reg<u32, _DOEPTSIZ>

0x3b0 - OTG_HS device endpoint-2 transfer size register

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