fdcan/
interrupt.rs

1//! Interrupt types.
2
3use core::ops;
4
5#[allow(unused_imports)] // for intra-doc links only
6use crate::{FdCan, Rx};
7
8macro_rules! declare_interrupts {
9    ($([$name:ident, $index:literal, $doc:expr],)*) => {
10        /// FdCAN interrupt sources.
11        ///
12        /// These can be individually enabled and disabled in the FdCAN
13        /// peripheral. Note that each FdCAN peripheral only exposes 2
14        /// interrupts to the microcontroller:
15        ///
16        /// FDCANx_INTR0,
17        /// FDCANx_INTR1,
18        ///
19        /// The interrupts available on each line can be configured using the
20        /// `[crate::config::FdCanConfig]` struct.
21        #[derive(Debug, Copy, Clone, Eq, PartialEq)]
22        #[non_exhaustive]
23        pub enum Interrupt {
24            $(
25                #[doc = $doc]
26                $name = 1 << $index
27            ),*
28        }
29
30        paste::paste! {
31            bitflags::bitflags! {
32                /// A set of FdCAN interrupts.
33                pub struct Interrupts: u32 {
34                    $(
35                        #[doc = $doc]
36                        const [< $name:snake:upper >] = 1 << $index;
37                    )*
38                }
39            }
40        }
41    };
42}
43
44// interrupts for g0 g4 l5
45#[cfg(feature = "fdcan_g0_g4_l5")]
46declare_interrupts!(
47    [RxFifo0NewMsg, 0, "Rx FIFO 0 has a new message"],
48    [RxFifo0Full, 1, "Rx FIFO 0 is full"],
49    [RxFifo0MsgLost, 2, "Rx FIFO 0 has lost a message"],
50    [RxFifo1NewMsg, 3, "Rx FIFO 1 has a new message"],
51    [RxFifo1Full, 4, "Rx FIFO 1 is full"],
52    [RxFifo1MsgLost, 5, "Rx FIFO 1 has lost a message"],
53    [
54        RxHighPrio,
55        6,
56        "A High Priority Message has been flagged by a filter"
57    ],
58    [TxComplete, 7, "Transmit has been completed"],
59    [TxCancel, 8, "Tx message has been cancelled"],
60    [TxEmpty, 9, "Tx Fifo is empty"],
61    [
62        TxEventNew,
63        10,
64        "An new Event has been received in the Tx Event Fifo"
65    ],
66    [TxEventFull, 11, "The TxEvent Fifo is full"],
67    [TxEventLost, 12, "An Tx Event has been lost"],
68    [TsWrapAround, 13, "Timestamp wrap around has occurred"],
69    [MsgRamAccessFailure, 14, "Message RAM access failure.
70The flag is set when the Rx handler:
71has not completed acceptance filtering or storage of an accepted message until the
72arbitration field of the following message has been received. In this case acceptance
73filtering or message storage is aborted and the Rx handler starts processing of the
74following message. was unable to write a message to the message RAM. In this case
75message storage is aborted.
76In both cases the FIFO put index is not updated. The partly stored message is overwritten
77when the next message is stored to this location.
78The flag is also set when the Tx Handler was not able to read a message from the Message
79RAM in time. In this case message transmission is aborted. In case of a Tx Handler access
80failure the FDCAN is switched into Restricted operation Mode (see Restricted operation
81mode)."],
82    [TimeoutOccurred, 15, "Timeout Occurred"],
83    [
84        ErrLogOverflow,
85        16,
86        "Overflow of CAN error logging counter occurred"
87    ],
88    [ErrPassive, 17, "Errr Passive"],
89    [WarningStatus, 18, "Warning Status"],
90    [BusOff, 19, "Bus_Off status"],
91    [WatchdogInt, 20, " Watchdog interrupt"],
92    [
93        ProtErrArbritation,
94        21,
95        "Protocol error in arbitration phase (nominal bit time is used)"
96    ],
97    [
98        ProtErrData,
99        22,
100        "Protocol error in data phase (data bit time is used)"
101    ],
102    [ReservedAccess, 23, "Access to reserved address"],
103);
104
105// interrupts for h7
106#[cfg(feature = "fdcan_h7")]
107declare_interrupts!(
108    [RxFifo0NewMsg, 0, "Rx FIFO 0 has a new message"],
109    [RxFifo0Watermark, 1, "Rx FIFO 0 watermark reached"],
110    [RxFifo0Full, 2, "Rx FIFO 0 is full"],
111    [RxFifo0MsgLost, 3, "Rx FIFO 0 has lost a message"],
112
113    [RxFifo1NewMsg, 4, "Rx FIFO 1 has a new message"],
114    [RxFifo1Watermark, 5, "Rx FIFO 1 watermark reached"],
115    [RxFifo1Full, 6, "Rx FIFO 1 is full"],
116    [RxFifo1MsgLost, 7, "Rx FIFO 1 has lost a message"],
117
118    [
119        RxHighPrio,
120        8,
121        "A High Priority Message has been flagged by a filter"
122    ],
123    [TxComplete, 9, "Transmit has been completed"],
124    [TxCancel, 10, "Tx message has been cancelled"],
125    [TxEmpty, 11, "Tx Fifo is empty"],
126    [
127        TxEventNew,
128        12,
129        "An new Event has been received in the Tx Event Fifo"
130    ],
131    [TxWatermark, 13, "TxEvent FIFO watermark reached"],
132    [TxEventFull, 14, "The TxEvent Fifo is full"],
133    [TxEventLost, 15, "An Tx Event has been lost"],
134    [TsWrapAround, 16, "Timestamp wrap around has occurred"],
135
136    [MsgRamAccessFailure, 17, "Message RAM access failure.
137The flag is set when the Rx handler:
138has not completed acceptance filtering or storage of an accepted message until the
139arbitration field of the following message has been received. In this case acceptance
140filtering or message storage is aborted and the Rx handler starts processing of the
141following message. was unable to write a message to the message RAM. In this case
142message storage is aborted.
143In both cases the FIFO put index is not updated. The partly stored message is overwritten
144when the next message is stored to this location.
145The flag is also set when the Tx Handler was not able to read a message from the Message
146RAM in time. In this case message transmission is aborted. In case of a Tx Handler access
147failure the FDCAN is switched into Restricted operation Mode (see Restricted operation
148mode)."],
149    [TimeoutOccurred, 18, "Timeout Occurred"],
150    [
151        ErrLogOverflow,
152        22,
153        "Overflow of CAN error logging counter occurred"
154    ],
155    [ErrPassive, 23, "Errr Passive"],
156    [WarningStatus, 24, "Warning Status"],
157    [BusOff, 25, "Bus_Off status"],
158    [WatchdogInt, 26, " Watchdog interrupt"],
159    [
160        ProtErrArbritation,
161        27,
162        "Protocol error in arbitration phase (nominal bit time is used)"
163    ],
164    [
165        ProtErrData,
166        28,
167        "Protocol error in data phase (data bit time is used)"
168    ],
169    [ReservedAccess, 29, "Access to reserved address"],
170);
171
172impl Interrupts {
173    /// No Interrupt masks selected
174    pub fn none() -> Self {
175        Self::from_bits_truncate(0)
176    }
177}
178
179impl From<Interrupt> for Interrupts {
180    #[inline]
181    fn from(i: Interrupt) -> Self {
182        Self::from_bits_truncate(i as u32)
183    }
184}
185
186/// Adds an interrupt to the interrupt set.
187impl ops::BitOrAssign<Interrupt> for Interrupts {
188    #[inline]
189    fn bitor_assign(&mut self, rhs: Interrupt) {
190        *self |= Self::from(rhs);
191    }
192}
193
194/// There are two interrupt lines for the FdCan
195/// The events linked to these can be configured
196/// see `[config::FdCanConfig]`
197#[derive(Debug, Copy, Clone, Eq, PartialEq)]
198pub enum InterruptLine {
199    /// Interrupt Line 0
200    _0 = 0,
201    /// Interrupt Line 1
202    _1 = 1,
203}
204
205#[cfg(test)]
206mod tests {
207    use super::*;
208
209    #[test]
210    fn interrupt_flags() {
211        assert_eq!(
212            Interrupts::from(Interrupt::TxComplete),
213            Interrupts::TX_COMPLETE
214        );
215        assert_eq!(Interrupts::from(Interrupt::TxEmpty), Interrupts::TX_EMPTY);
216
217        let mut ints = Interrupts::RX_FIFO0_FULL;
218        ints |= Interrupt::RxFifo1Full;
219        assert_eq!(ints, Interrupts::RX_FIFO0_FULL | Interrupts::RX_FIFO1_FULL);
220    }
221}
fdcan/interrupt.rs

fdcan/
interrupt.rs
