Expand description
To use PCI, use PciAccess::new_pci.
To use PCIe, use PciAccess::new_pcie.
Then you can scan buses. For each bus, you can scan devices. For each device, you can scan functions. For each function, you can scan BARs, capabilities, and general info.
You can also find and configure MSI (Message Signaled Interrupts)
Structs§
- Apic
MsiMessage Address - See Intel SDM -> Volume 3 -> 12.11.1 Message Address Register Format
- Apic
MsiMessage Data - See Intel SDM -> Volume 3 -> 12.11.2 Message Data Register Format
- BarCommon
- Capabilities
- Capability
- Command
Register - Header
Type Byte - Interrupt
Info - IoBar
Info - IoSpace
Bar - Mcfg
Entry - Memory
BarAddr AndSize U32 - Memory
BarAddr AndSize U64 - Memory
BarInfo - Memory
Space Bar - Message
Control Register - Msi
- MsiX
- MsiX
Location - The table and pending bit array are stored inside a BAR. The BAR index and offset inside the BAR are encoded in a `u32``. PCI Local Bus Specification Rev. 3.0 -> 6.8.2.4. Table Offset/Table BIR for MSI-X
- MsiX
Message Control - PCI Local Bus Specification Rev. 3.0 -> 6.8.2.3. Message Control for MSI-X
- MsiX
Pending BitArray - This array tells you which interrupts are pending delivery. This is read-only to the kernel.
- MsiX
Table - MsiX
Table Entry - MsiX
Vector Control - PCI Local Bus Specification Rev. 3.0 -> 6.8.2.9. Vector Control for MSI-X Table Entries
- Pci
- PciBus
- PciDevice
- PciFunction
- Pcie
- Phys
Addr - A 64-bit physical memory address.
- Volatile
Ptr - Wraps a pointer to make accesses to the referenced value volatile.