Crate extract_rust_hdl_interface
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generate_rust_hdl_module
This crate provides a extract_rust_hdl_interface
function that extracts all the info you need to generate a rust-hdl module from a Verilog module.
The function does not actually generate code it just extracts the interface. It is mainly meant be used through the wrap_verilog!
macro.
Structs
- Represents a rust-hdl module.
- Represents a signal in a rust-hdl module.
Enums
- The type of a signal.
Functions
- Extract all information needed to generate a wrapping rust-hdl module from a Verilog module.