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Crate eth_phy_lan867x

Crate eth_phy_lan867x 

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#![no_std] MDIO driver for the Microchip LAN867x family of 10BASE-T1S Ethernet PHYs (IEEE 802.3cg-2019 Clause 147):

  • LAN8670 (32-VQFN, MII or RMII)
  • LAN8671 (24-VQFN, RMII only) — JetHome hardware target
  • LAN8672 (36-VQFN, MII only)

Implements eth_mdio_phy::PhyDriver, so any MAC that exposes eth_mdio_phy::MdioBus can drive the chip.

10BASE-T1S is single-pair, half-duplex, multidrop Ethernet — quite different from the point-to-point 10/100BASE-T flavours covered by eth-phy-lan87xx. Notably:

  • There is no auto-negotiation (BMCR.AUTO_NEG_EN is hard-wired 0).
  • BMSR.LINK_STATUS is hard-wired 1 — useless for link detection. Use PhyLan867x::poll_link, which reads PLCA_STS.PST when PLCA is enabled.
  • Most operational state lives in MMD-31 (Vendor Specific 2), accessed via the IEEE Annex 22D MMDCTRL/MMDAD indirection.
  • The chip ships in a multidrop-disabled state — driver init() sets T1SPMACTL.MDE = 1.

Reference datasheet: Microchip DS60001573C (silicon revision 2, product revision B1).

Re-exports§

pub use plca::PlcaConfig;
pub use plca::PlcaError;
pub use plca::PlcaStatus;

Modules§

plca
PLCA (Physical Layer Collision Avoidance) configuration types.

Structs§

PhyLan867x
LAN867x PHY driver (software-only, no reset pin).
PhyLan867xWithReset
LAN867x PHY driver with a hardware reset pin.

Enums§

Chip
Concrete LAN867x family member, identified at PhyLan867x::init time from STRAP_CTRL0.PKGTYP.