pub const CACHE_LINE: usize = 64; // 64usizeExpand description
Cache-line size in bytes. Per-hart outputs are placed one-per-line so that
distinct harts never write the same line: false sharing silently corrupts
data on this software-coherent architecture. Defined once in et-abi and
shared with the host, so the two sides cannot disagree on the stride.
ET-SoC-1 cache-line size, in bytes.
Per-hart outputs are laid out at this stride on both sides: the host strides
its padded arrays by it and the device writes each hart’s cell at
base + hart * CACHE_LINE. Defining it once here keeps the two from drifting,
which on this software-coherent part would cause silent false-sharing
corruption.