Module cache 

L1 cache management for software-coherent cross-hart sharing.

Provides cache::cache_writeback, cache::cache_invalidate, and cache::cache_flush for flushing and invalidating L1 data cache lines by virtual address and byte length. Lower-level _to variants accept an explicit cache::CacheDest when targeting L2 or L3 rather than DDR.

All functions use the flush_va (CSR 0x8BF) and evict_va (CSR 0x89F) hardware operations as documented in the Ainekko SDK cacheops.h. Cache management operations for the ET-SoC-1 Minion processor.

The ET-SoC-1 implements a software-coherent memory model: the RISC-V fence instruction orders CPU-visible stores but does not flush dirty L1 data cache lines to L2 or DDR. Cross-hart, cross-shire, and host-visible coherence therefore require explicit cache management via dedicated CSRs.

Cache hierarchy

Each Minion core has a private L1 data cache with 64-byte lines. The L2 is shared among all Minions in a shire (512 KB on aifoundry3). The L3 is shared across all compute shires (32 MB on aifoundry3). Host DMA reads bypass all Minion caches and observe only DDR.

Producer/consumer protocol

Per PRM Section 8.1.3, software must fence before a cache op (to commit all prior CPU stores to L1) and issue TensorWait(CacheOp) after (to guarantee the op completed before any subsequent memory access to the affected lines). The high-level functions below handle the TensorWait internally; only the preceding fence is the caller’s responsibility.

// Hart A (producer):
// ... write data ...
fence();                                          // commit stores to L1
unsafe { cache_writeback(ptr as usize, len); }  // flush L1 to DDR + TensorWait

// <synchronisation, e.g. via a shared flag + fence on both sides>

// Hart B (consumer):
fence();                                          // receive synchronisation
unsafe { cache_invalidate(ptr as usize, len); }  // discard stale L1 + TensorWait
// ... read data ...

Use [cache_flush] when a region may contain both dirty (locally modified) and stale lines, performing writeback then invalidation atomically at the function level.

Cache levels

The high-level functions [cache_writeback], [cache_invalidate], and [cache_flush] propagate to main memory ([CacheDest::Mem]), which is the safest choice for cross-shire and host-DMA coherence. The lower-level _to variants accept an explicit [CacheDest] for intra-shire operations that need only reach L2.

Enums

CacheDest

Target cache hierarchy level for cache management operations.

Constants

CSR_EVICT_VA

evict_va CSR: evicts cache lines by virtual address up to a target level.

CSR_FLUSH_VA

flush_va CSR: writes back dirty cache lines by virtual address to a target level.

Functions

cache_flush^⚠

Writes back then invalidates L1 cache lines in [addr, addr + len).

cache_invalidate^⚠

Invalidates (evicts) L1 cache lines in [addr, addr + len).

cache_invalidate_to^⚠

Invalidates cache lines in [addr, addr + len), evicting to dst.

cache_writeback^⚠

Writes back dirty L1 cache lines in [addr, addr + len) to main memory.

cache_writeback_to^⚠

Writes back dirty cache lines in [addr, addr + len) to dst.