Module tensor 

Tensor-extension intrinsics, all encoded as RISC-V csrrw writes (PRM Ch. 9).

Load: tensor::tensor_load, tensor::tensor_load_b, tensor::tensor_load_l2. FMA (fp32): tensor::fma32_xs + tensor::tensor_fma32. FMA (fp16 -> fp32): tensor::fma16a32_xs + tensor::tensor_fma16a32 (CSR 0x801, bits 3:1 = 001). GEMM (int8 -> int32): tensor::ima8a32_xs + tensor::tensor_ima8a32 (CSR 0x801, bits 3:1 = 011; DST selects FP-register or TenC output). Store (from FP regs): tensor::tensor_store. Store (from scratchpad): tensor::tensor_store_from_scp (CSR 0x87F, bit 48 = 1; reads L1 scratchpad lines directly to DRAM). Reduction: tensor::tensor_send / tensor::tensor_recv (CSR 0x800; hart-to-hart FP register exchange with optional combine via tensor::ReduceFunct). Synchronisation: tensor::tensor_wait / tensor::TensorEvent. Tensor-extension intrinsics for the ET-SoC-1 Minion core.

All tensor instructions on the ET-SoC-1 are encoded as standard RISC-V csrrw xd, <csr>, xs writes (see PRM Chapter 9). No custom opcode or target-feature extension is required: riscv64imac suffices because the operand registers are ordinary integer GPRs (the source value xs is an integer register; the FP register file is accessed implicitly by the tensor co-processor hardware, not by the instruction encoding).

Concurrency model

The tensor co-processor operates independently of the RISC-V hart’s integer pipeline. Issuing a tensor instruction initiates an asynchronous operation; the hart must call [tensor_wait] with the appropriate [TensorEvent] before reading results or reusing the scratchpad. The ordering guarantees are:

• TensorWait(Load0) before tensor_fma32 / tensor_fma16a32 / tensor_ima8a32: scratchpad A (and B when TENB=0) is populated.
• TensorWait(Fma) before tensor_store / tensor_store_from_scp: FP register file (or TenC for IMA8A32 with DST=0) holds final C.
• TensorWait(Store) drains only tensor store DMA; prefer it over a full fence rw, rw when only tensor-store ordering is required.
• TensorWait(LoadL2_0) or TensorWait(LoadL2_1) after [tensor_load_l2]: the shire L2 prefetch has completed.
• TensorWait(CacheOp) after cache_writeback / cache_invalidate / cache_flush: all L1 cache management operations have completed.
• fence rw, rw (via crate::fence) after the final store: writes are visible to other Minions and the DMA engine before the kernel returns.

Scratchpad layout

Each Minion has a private 48-line L1 scratchpad (3 072 bytes). Only the primary hart of the Minion (hart 0, i.e. mhartid & 1 == 0) should issue tensor load/store/FMA instructions; the companion hart (hart 1) must not touch the same scratchpad lines concurrently.

Structs

TensorError

Tensor co-processor error status, returned by check_tensor_error.

Enums

ReduceFunct

Reduction function selector for tensor_recv.

TensorEvent

Tensor co-processor synchronisation events for tensor_wait.

Constants

CSR_TENSOR_ERROR

TensorError CSR (tensor_error): latched error flags from the co-processor. (PRM Table 9-1: 0x808, not 0x831)

CSR_TENSOR_FMA

TensorFMA CSR (tensor_fma): selects the FMA variant via xs bits 3:1. (PRM Table 9-7: TensorFMA32 = 3:1 000, TensorFMA16A32 = 001, …)

CSR_TENSOR_LOAD

TensorLoad / TensorLoadB CSR (tensor_load): load from memory to the L1 scratchpad (xs bit 52 = 0) or to the TenB register file (bit 52 = 1).

CSR_TENSOR_LOAD_L2

TensorLoadL2Scp CSR: loads rows from memory to the shire L2 cache without consuming any L1 scratchpad lines. Useful for prefetching A strips while the current k-loop tile executes, so the subsequent tensor_load (L1 fill) completes from L2 rather than DRAM.

CSR_TENSOR_MASK

TensorMask CSR (tensor_mask): per-row enable bits for the A tile. (PRM Table 9-1: 0x805, not 0x832)

CSR_TENSOR_REDUCE

TensorReduce CSR (tensor_reduce): hart-to-hart register-file exchange. xs bits 1:0 select the variant: TensorSend=00, TensorRecv=01, TensorBroadcast=10, TensorReduce=11. (PRM Table 9-7: 0x800)

CSR_TENSOR_STORE

TensorStore CSR (tensor_store): store from FP registers (bit 48 = 0) or from the L1 scratchpad (bit 48 = 1 = TensorStoreFromScp) to memory. (PRM Table 9-7: 0x87F, not 0x83E)

CSR_TENSOR_WAIT

TensorWait CSR (tensor_wait): stalls the hart until the requested event.

Functions

check_tensor_error

Check the tensor co-processor error register and return a typed result.

fma16a32_xs

Build the xs value for a TensorFMA16A32 instruction.

fma32_xs

Build the xs value for a TensorFMA32 instruction.

ima8a32_xs

Build the xs value for a TensorIMA8A32 instruction.

set_tensor_mask

Write the per-row enable mask for the next TensorFMA.

tensor_error

Read the tensor co-processor error status register.

tensor_fma32^⚠

Initiate an asynchronous TensorFMA32.

tensor_fma16a32^⚠

Initiate an asynchronous TensorFMA16A32.

tensor_ima8a32^⚠

Initiate an asynchronous TensorIMA8A32.

tensor_load^⚠

Initiate an asynchronous TensorLoad from memory into the L1 scratchpad.

tensor_load_b^⚠

Initiate an asynchronous TensorLoadB from memory into the TenB register file.

tensor_load_l2^⚠

Initiate an asynchronous TensorLoadL2Scp from memory into the shire L2 cache.

tensor_recv^⚠

Initiate an asynchronous TensorRecv.

tensor_send^⚠

Initiate an asynchronous TensorSend.

tensor_store^⚠

Initiate an asynchronous TensorStore from the FP register file to memory.

tensor_store_from_scp^⚠

Initiate an asynchronous TensorStoreFromScp to memory from the L1 scratchpad.

tensor_wait

Stall the hart until the specified tensor co-processor event fires.