Module pmu 

Performance Monitoring Unit (PMU) counter API.

Provides pmu::pmu_read (reads hpmcounterN in U-mode) and the pmu::PmuEvent event-code enum for characterising tensor kernel behaviour. Performance Monitoring Unit (PMU) counter API for the ET-SoC-1 Minion core.

The ET-SoC-1 implements the RISC-V Zihpm extension: hardware performance counters accessible from U-mode via the hpmcounterN CSRs (PRM Chapter 8). Each counter is a 64-bit read-only accumulator that increments on each occurrence of the event assigned to it by firmware (or pmu_configure if U-mode write access to mhpmeventN is confirmed).

Available counters

• hpmcounter3 (CSR 0xC03): also read by crate::timestamp as a cycle counter. Whether the assigned event is cycle or a custom PMU event depends on the firmware’s mhpmeventN configuration.
• hpmcounter4 .. hpmcounter31 (CSR 0xC04 .. 0xC1F): available for application use subject to firmware assignment.

Usage pattern

use et_kernel::pmu::{PmuEvent, pmu_read};

// Read counter 4 before and after a tensor operation; the delta is the
// number of TFMA_WAIT_TENB events that occurred (assuming firmware assigned
// PmuEvent::TfmaWaitTenb to counter 4 via mhpmevent4).
let before = pmu_read(4);
// ... tensor operations ...
let after  = pmu_read(4);
let delta  = after.wrapping_sub(before);

Enums

PmuEvent

PMU event codes for the ET-SoC-1. The value is written to mhpmeventN (CSR 0x320 + N) to select what counter N accumulates.

Functions

pmu_read

Read hardware performance counter N (hpmcounterN, CSR 0xC03 + (N-3)).

pmu_read_cycle

Read the cycle counter (CSR 0xC00).

pmu_read_instret

Read the instret counter (CSR 0xC02).