Crate et_abi 

Shared host/device ABI for the ET-SoC-1: the kernel-launch argument structs, defined once and used by both the host launcher and the device kernel.

Kernel arguments are passed by pointer: the host stages an argument struct in device memory and the firmware delivers its address to the kernel (in a0). Because both the host (x86-64) and the device (RV64) are little-endian, the in-memory #[repr(C)] layout is the wire layout, so no explicit serialisation is needed – the host takes the struct’s bytes and the kernel reinterprets the pointer. Defining each struct here keeps the two sides from drifting (mismatched field order, sizes, or padding).

Structs

CachePadded

A wrapper that aligns T to a cache-line boundary.

GemmArgs

Arguments for the single-precision general matrix multiplication (sGEMM) kernel (sgemm-rs), implementing C = alphaAB + beta*C.

ReduceArgs

Arguments for the data-parallel reduction kernel (reduce-rs).

Constants

CACHE_LINE

ET-SoC-1 cache-line size, in bytes.

GEMM_TILE_K

Inner-dimension (K) slice processed per TensorFMA32 call. Limited to 16 f32 values per A-matrix row fitting in one 64-byte scratchpad line (ACOLS field is 4-bit, max 15 -> 16 columns).

GEMM_TILE_M

Number of C output rows computed per tile by TensorFMA32. Equals the maximum AROWS+1 value (4-bit field, max 15 -> 16 rows).

GEMM_TILE_N

Number of f32 output columns produced per TensorFMA32 call (BCOLS=3 gives 4*(3+1) = 16 columns). Each tile row occupies exactly 64 bytes in the FP register file. N need not be a multiple of this value; the last tile column may be partial, with the hardware writing 64 bytes per row regardless – the caller reads only the N valid columns from the 64-byte-aligned allocation.

HARTS_PER_NEIGHBOURHOOD

Harts per neighbourhood on the ET-SoC-1 (architectural constant).

HARTS_PER_SHIRE

Harts per compute shire on the ET-SoC-1 (architectural constant).

MINIONS_PER_SHIRE

Minion cores per compute shire on the ET-SoC-1. Each shire has 32 dual-threaded Minion cores (64 harts total).

SCP_LINES

Number of addressable cache lines in each Minion’s L1 scratchpad. TensorLoad START field is 6 bits, spanning lines 0..47 inclusive.

SCP_LINE_BYTES

Bytes per L1 scratchpad line (one cache line).

TENSOR_ALIGN

Required alignment for all matrix pointers and row strides used with the ET-SoC-1 tensor-load/store instructions. TensorLoad and TensorStore each require the source or destination address to be 64-byte aligned.

Traits

DeviceArgs

A plain-old-data kernel-argument struct exchanged between host and device.