espflash/target/efuse/
esp32p4.rs

1//! eFuse field definitions for the esp32p4
2//!
3//! This file was automatically generated, please do not edit it manually!
4//!
5//! Generated: 2025-12-08 14:48
6//! Version:   f7765f0ac3faf4b54f8c1f064307522c
7
8#![allow(unused)]
9
10use super::{EfuseBlock, EfuseField};
11
12/// All eFuse blocks available on this device.
13pub(crate) const BLOCKS: &[EfuseBlock] = &[
14    EfuseBlock {
15        index: 0u8,
16        length: 6u8,
17        read_address: 0x5012d02cu32,
18        write_address: 0x5012d000u32,
19    },
20    EfuseBlock {
21        index: 1u8,
22        length: 6u8,
23        read_address: 0x5012d044u32,
24        write_address: 0x5012d000u32,
25    },
26    EfuseBlock {
27        index: 2u8,
28        length: 8u8,
29        read_address: 0x5012d05cu32,
30        write_address: 0x5012d000u32,
31    },
32    EfuseBlock {
33        index: 3u8,
34        length: 8u8,
35        read_address: 0x5012d07cu32,
36        write_address: 0x5012d000u32,
37    },
38    EfuseBlock {
39        index: 4u8,
40        length: 8u8,
41        read_address: 0x5012d09cu32,
42        write_address: 0x5012d000u32,
43    },
44    EfuseBlock {
45        index: 5u8,
46        length: 8u8,
47        read_address: 0x5012d0bcu32,
48        write_address: 0x5012d000u32,
49    },
50    EfuseBlock {
51        index: 6u8,
52        length: 8u8,
53        read_address: 0x5012d0dcu32,
54        write_address: 0x5012d000u32,
55    },
56    EfuseBlock {
57        index: 7u8,
58        length: 8u8,
59        read_address: 0x5012d0fcu32,
60        write_address: 0x5012d000u32,
61    },
62    EfuseBlock {
63        index: 8u8,
64        length: 8u8,
65        read_address: 0x5012d11cu32,
66        write_address: 0x5012d000u32,
67    },
68    EfuseBlock {
69        index: 9u8,
70        length: 8u8,
71        read_address: 0x5012d13cu32,
72        write_address: 0x5012d000u32,
73    },
74    EfuseBlock {
75        index: 10u8,
76        length: 8u8,
77        read_address: 0x5012d15cu32,
78        write_address: 0x5012d000u32,
79    },
80];
81
82/// Defined eFuse registers and commands
83pub(crate) mod defines {
84    use super::super::EfuseBlockErrors;
85    pub(crate) const BLOCK_ERRORS: &[EfuseBlockErrors] = &[
86        EfuseBlockErrors {
87            err_num_reg: 0x5012d17cu32,
88            err_num_mask: None,
89            err_num_offset: None,
90            fail_bit_reg: 0x5012d17cu32,
91            fail_bit_offset: None,
92        },
93        EfuseBlockErrors {
94            err_num_reg: 0x5012d1c0u32,
95            err_num_mask: Some(0x7u32),
96            err_num_offset: Some(0x0u32),
97            fail_bit_reg: 0x5012d1c0u32,
98            fail_bit_offset: Some(0x3u32),
99        },
100        EfuseBlockErrors {
101            err_num_reg: 0x5012d1c0u32,
102            err_num_mask: Some(0x7u32),
103            err_num_offset: Some(0x4u32),
104            fail_bit_reg: 0x5012d1c0u32,
105            fail_bit_offset: Some(0x7u32),
106        },
107        EfuseBlockErrors {
108            err_num_reg: 0x5012d1c0u32,
109            err_num_mask: Some(0x7u32),
110            err_num_offset: Some(0x8u32),
111            fail_bit_reg: 0x5012d1c0u32,
112            fail_bit_offset: Some(0xbu32),
113        },
114        EfuseBlockErrors {
115            err_num_reg: 0x5012d1c0u32,
116            err_num_mask: Some(0x7u32),
117            err_num_offset: Some(0xcu32),
118            fail_bit_reg: 0x5012d1c0u32,
119            fail_bit_offset: Some(0xfu32),
120        },
121        EfuseBlockErrors {
122            err_num_reg: 0x5012d1c0u32,
123            err_num_mask: Some(0x7u32),
124            err_num_offset: Some(0x10u32),
125            fail_bit_reg: 0x5012d1c0u32,
126            fail_bit_offset: Some(0x13u32),
127        },
128        EfuseBlockErrors {
129            err_num_reg: 0x5012d1c0u32,
130            err_num_mask: Some(0x7u32),
131            err_num_offset: Some(0x14u32),
132            fail_bit_reg: 0x5012d1c0u32,
133            fail_bit_offset: Some(0x17u32),
134        },
135        EfuseBlockErrors {
136            err_num_reg: 0x5012d1c0u32,
137            err_num_mask: Some(0x7u32),
138            err_num_offset: Some(0x18u32),
139            fail_bit_reg: 0x5012d1c0u32,
140            fail_bit_offset: Some(0x1bu32),
141        },
142        EfuseBlockErrors {
143            err_num_reg: 0x5012d1c0u32,
144            err_num_mask: Some(0x7u32),
145            err_num_offset: Some(0x1cu32),
146            fail_bit_reg: 0x5012d1c0u32,
147            fail_bit_offset: Some(0x1fu32),
148        },
149        EfuseBlockErrors {
150            err_num_reg: 0x5012d1c4u32,
151            err_num_mask: Some(0x7u32),
152            err_num_offset: Some(0x0u32),
153            fail_bit_reg: 0x5012d1c4u32,
154            fail_bit_offset: Some(0x3u32),
155        },
156        EfuseBlockErrors {
157            err_num_reg: 0x5012d1c4u32,
158            err_num_mask: Some(0x7u32),
159            err_num_offset: Some(0x4u32),
160            fail_bit_reg: 0x5012d1c4u32,
161            fail_bit_offset: Some(0x7u32),
162        },
163    ];
164    pub(crate) const EFUSE_READ_CMD: u32 = 0x1;
165    pub(crate) const EFUSE_WR_TIM_CONF1_REG: u32 = 0x5012d1f0;
166    pub(crate) const EFUSE_DAC_CLK_DIV_M: u32 = 0xff;
167    pub(crate) const EFUSE_PGM_DATA0_REG: u32 = 0x5012d000;
168    pub(crate) const EFUSE_CHECK_VALUE0_REG: u32 = 0x5012d020;
169    pub(crate) const EFUSE_DATE_REG: u32 = 0x5012d1fc;
170    pub(crate) const EFUSE_RD_TIM_CONF_REG: u32 = 0x5012d1ec;
171    pub(crate) const EFUSE_CMD_REG: u32 = 0x5012d1d4;
172    pub(crate) const EFUSE_RD_REPEAT_ERR0_REG: u32 = 0x5012d17c;
173    pub(crate) const EFUSE_WR_TIM_CONF2_REG: u32 = 0x5012d1f4;
174    pub(crate) const CODING_SCHEME_REPEAT: u32 = 0x2;
175    pub(crate) const EFUSE_PWR_ON_NUM_S: u32 = 0x8;
176    pub(crate) const EFUSE_DAC_CONF_REG: u32 = 0x5012d1e8;
177    pub(crate) const EFUSE_RD_RS_ERR1_REG: u32 = 0x5012d1c4;
178    pub(crate) const EFUSE_CLK_REG: u32 = 0x5012d1c8;
179    pub(crate) const EFUSE_DAC_NUM_M: u32 = 0x1fe00;
180    pub(crate) const EFUSE_PGM_CMD_MASK: u32 = 0x3;
181    pub(crate) const EFUSE_WRITE_OP_CODE: u32 = 0x5a5a;
182    pub(crate) const EFUSE_CONF_REG: u32 = 0x5012d1cc;
183    pub(crate) const CODING_SCHEME_NONE_RECOVERY: u32 = 0x3;
184    pub(crate) const CODING_SCHEME_NONE: u32 = 0x0;
185    pub(crate) const EFUSE_DAC_CLK_DIV_S: u32 = 0x0;
186    pub(crate) const CODING_SCHEME_RS: u32 = 0x4;
187    pub(crate) const EFUSE_RD_REPEAT_ERR3_REG: u32 = 0x5012d188;
188    pub(crate) const EFUSE_PWR_OFF_NUM_M: u32 = 0xffff;
189    pub(crate) const EFUSE_RD_REPEAT_ERR2_REG: u32 = 0x5012d184;
190    pub(crate) const EFUSE_DAC_NUM_S: u32 = 0x9;
191    pub(crate) const EFUSE_PGM_CMD: u32 = 0x2;
192    pub(crate) const EFUSE_RD_REPEAT_ERR1_REG: u32 = 0x5012d180;
193    pub(crate) const EFUSE_READ_OP_CODE: u32 = 0x5aa5;
194    pub(crate) const EFUSE_STATUS_REG: u32 = 0x5012d1d0;
195    pub(crate) const EFUSE_MEM_SIZE: u32 = 0x200;
196    pub(crate) const EFUSE_PWR_OFF_NUM_S: u32 = 0x0;
197    pub(crate) const EFUSE_RD_REPEAT_ERR4_REG: u32 = 0x5012d18c;
198    pub(crate) const EFUSE_PWR_ON_NUM_M: u32 = 0xffff00;
199    pub(crate) const EFUSE_RD_RS_ERR0_REG: u32 = 0x5012d1c0;
200    pub(crate) const CODING_SCHEME_34: u32 = 0x1;
201}
202
203/// Disable programming of individual eFuses
204pub const WR_DIS: EfuseField = EfuseField::new(0, 0, 0, 32);
205/// Disable reading from BlOCK4-10
206pub const RD_DIS: EfuseField = EfuseField::new(0, 1, 32, 7);
207/// Enable usb device exchange pins of D+ and D-
208pub const USB_DEVICE_EXCHG_PINS: EfuseField = EfuseField::new(0, 1, 39, 1);
209/// Enable usb otg11 exchange pins of D+ and D-
210pub const USB_OTG11_EXCHG_PINS: EfuseField = EfuseField::new(0, 1, 40, 1);
211/// Represents whether the function of usb switch to jtag is disabled or
212/// enabled. 1: disabled. 0: enabled
213pub const DIS_USB_JTAG: EfuseField = EfuseField::new(0, 1, 41, 1);
214/// Represents whether power glitch function is enabled. 1: enabled. 0: disabled
215pub const POWERGLITCH_EN: EfuseField = EfuseField::new(0, 1, 42, 1);
216/// Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0:
217/// enabled
218pub const DIS_USB_SERIAL_JTAG: EfuseField = EfuseField::new(0, 1, 43, 1);
219/// Represents whether the function that forces chip into download mode is
220/// disabled or enabled. 1: disabled. 0: enabled
221pub const DIS_FORCE_DOWNLOAD: EfuseField = EfuseField::new(0, 1, 44, 1);
222/// Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix
223/// during boot_mode_download
224pub const SPI_DOWNLOAD_MSPI_DIS: EfuseField = EfuseField::new(0, 1, 45, 1);
225/// Represents whether TWAI function is disabled or enabled. 1: disabled. 0:
226/// enabled
227pub const DIS_TWAI: EfuseField = EfuseField::new(0, 1, 46, 1);
228/// Represents whether the selection between usb_to_jtag and pad_to_jtag through
229/// strapping gpio34 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are
230/// equal to 0 is enabled or disabled. 1: enabled. 0: disabled
231pub const JTAG_SEL_ENABLE: EfuseField = EfuseField::new(0, 1, 47, 1);
232/// Represents whether JTAG is disabled in soft way. Odd number: disabled. Even
233/// number: enabled
234pub const SOFT_DIS_JTAG: EfuseField = EfuseField::new(0, 1, 48, 3);
235/// Represents whether JTAG is disabled in the hard way(permanently). 1:
236/// disabled. 0: enabled
237pub const DIS_PAD_JTAG: EfuseField = EfuseField::new(0, 1, 51, 1);
238/// Represents whether flash encrypt function is disabled or enabled(except in
239/// SPI boot mode). 1: disabled. 0: enabled
240pub const DIS_DOWNLOAD_MANUAL_ENCRYPT: EfuseField = EfuseField::new(0, 1, 52, 1);
241/// USB intphy of usb device signle-end input high threshold; 1.76V to 2V. Step
242/// by 80mV
243pub const USB_DEVICE_DREFH: EfuseField = EfuseField::new(0, 1, 53, 2);
244/// USB intphy of usb otg11 signle-end input high threshold; 1.76V to 2V. Step
245/// by 80mV
246pub const USB_OTG11_DREFH: EfuseField = EfuseField::new(0, 1, 55, 2);
247/// TBD
248pub const USB_PHY_SEL: EfuseField = EfuseField::new(0, 1, 57, 1);
249/// Set this bit to control validation of HUK generate mode. Odd of 1 is
250/// invalid; even of 1 is valid
251pub const KM_HUK_GEN_STATE: EfuseField = EfuseField::new(0, 1, 58, 9);
252/// Set bits to control key manager random number switch cycle. 0: control by
253/// register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles
254pub const KM_RND_SWITCH_CYCLE: EfuseField = EfuseField::new(0, 2, 67, 2);
255/// Set each bit to control whether corresponding key can only be deployed once.
256/// 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds
257pub const KM_DEPLOY_ONLY_ONCE: EfuseField = EfuseField::new(0, 2, 69, 4);
258/// Set each bit to control whether corresponding key must come from key
259/// manager.. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3:
260/// ds
261pub const FORCE_USE_KEY_MANAGER_KEY: EfuseField = EfuseField::new(0, 2, 73, 4);
262/// Set this bit to disable software written init key; and force use
263/// efuse_init_key
264pub const FORCE_DISABLE_SW_INIT_KEY: EfuseField = EfuseField::new(0, 2, 77, 1);
265/// Set this bit to configure flash encryption use xts-128 key; else use xts-256
266/// key
267pub const XTS_KEY_LENGTH_256: EfuseField = EfuseField::new(0, 2, 78, 1);
268/// Reserved; it was created by set_missed_fields_in_regs func
269pub const RESERVE_0_79: EfuseField = EfuseField::new(0, 2, 79, 1);
270/// Represents whether RTC watchdog timeout threshold is selected at startup. 1:
271/// selected. 0: not selected
272pub const WDT_DELAY_SEL: EfuseField = EfuseField::new(0, 2, 80, 2);
273/// Enables flash encryption when 1 or 3 bits are set and disables otherwise
274pub const SPI_BOOT_CRYPT_CNT: EfuseField = EfuseField::new(0, 2, 82, 3);
275/// Revoke 1st secure boot key
276pub const SECURE_BOOT_KEY_REVOKE0: EfuseField = EfuseField::new(0, 2, 85, 1);
277/// Revoke 2nd secure boot key
278pub const SECURE_BOOT_KEY_REVOKE1: EfuseField = EfuseField::new(0, 2, 86, 1);
279/// Revoke 3rd secure boot key
280pub const SECURE_BOOT_KEY_REVOKE2: EfuseField = EfuseField::new(0, 2, 87, 1);
281/// Represents the purpose of Key0
282pub const KEY_PURPOSE_0: EfuseField = EfuseField::new(0, 2, 88, 4);
283/// Represents the purpose of Key1
284pub const KEY_PURPOSE_1: EfuseField = EfuseField::new(0, 2, 92, 4);
285/// Represents the purpose of Key2
286pub const KEY_PURPOSE_2: EfuseField = EfuseField::new(0, 3, 96, 4);
287/// Represents the purpose of Key3
288pub const KEY_PURPOSE_3: EfuseField = EfuseField::new(0, 3, 100, 4);
289/// Represents the purpose of Key4
290pub const KEY_PURPOSE_4: EfuseField = EfuseField::new(0, 3, 104, 4);
291/// Represents the purpose of Key5
292pub const KEY_PURPOSE_5: EfuseField = EfuseField::new(0, 3, 108, 4);
293/// Represents the spa secure level by configuring the clock random divide mode
294pub const SEC_DPA_LEVEL: EfuseField = EfuseField::new(0, 3, 112, 2);
295/// Represents whether hardware random number k is forced used in ESDCA. 1:
296/// force used. 0: not force used
297pub const ECDSA_ENABLE_SOFT_K: EfuseField = EfuseField::new(0, 3, 114, 1);
298/// Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled
299pub const CRYPT_DPA_ENABLE: EfuseField = EfuseField::new(0, 3, 115, 1);
300/// Represents whether secure boot is enabled or disabled. 1: enabled. 0:
301/// disabled
302pub const SECURE_BOOT_EN: EfuseField = EfuseField::new(0, 3, 116, 1);
303/// Represents whether revoking aggressive secure boot is enabled or disabled.
304/// 1: enabled. 0: disabled
305pub const SECURE_BOOT_AGGRESSIVE_REVOKE: EfuseField = EfuseField::new(0, 3, 117, 1);
306/// Reserved; it was created by set_missed_fields_in_regs func
307pub const RESERVE_0_118: EfuseField = EfuseField::new(0, 3, 118, 1);
308/// The type of interfaced flash. 0: four data lines; 1: eight data lines
309pub const FLASH_TYPE: EfuseField = EfuseField::new(0, 3, 119, 1);
310/// Set flash page size
311pub const FLASH_PAGE_SIZE: EfuseField = EfuseField::new(0, 3, 120, 2);
312/// Set this bit to enable ecc for flash boot
313pub const FLASH_ECC_EN: EfuseField = EfuseField::new(0, 3, 122, 1);
314/// Set this bit to disable download via USB-OTG
315pub const DIS_USB_OTG_DOWNLOAD_MODE: EfuseField = EfuseField::new(0, 3, 123, 1);
316/// Represents the flash waiting time after power-up; in unit of ms. When the
317/// value less than 15; the waiting time is the programmed value. Otherwise; the
318/// waiting time is 2 times the programmed value
319pub const FLASH_TPUW: EfuseField = EfuseField::new(0, 3, 124, 4);
320/// Represents whether Download mode is disabled or enabled. 1: disabled. 0:
321/// enabled
322pub const DIS_DOWNLOAD_MODE: EfuseField = EfuseField::new(0, 4, 128, 1);
323/// Represents whether direct boot mode is disabled or enabled. 1: disabled. 0:
324/// enabled
325pub const DIS_DIRECT_BOOT: EfuseField = EfuseField::new(0, 4, 129, 1);
326/// Represents whether print from USB-Serial-JTAG is disabled or enabled. 1:
327/// disabled. 0: enabled
328pub const DIS_USB_SERIAL_JTAG_ROM_PRINT: EfuseField = EfuseField::new(0, 4, 130, 1);
329/// TBD
330pub const LOCK_KM_KEY: EfuseField = EfuseField::new(0, 4, 131, 1);
331/// Represents whether the USB-Serial-JTAG download function is disabled or
332/// enabled. 1: disabled. 0: enabled
333pub const DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE: EfuseField = EfuseField::new(0, 4, 132, 1);
334/// Represents whether security download is enabled or disabled. 1: enabled. 0:
335/// disabled
336pub const ENABLE_SECURITY_DOWNLOAD: EfuseField = EfuseField::new(0, 4, 133, 1);
337/// Represents the type of UART printing. 00: force enable printing. 01: enable
338/// printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is
339/// reset at high level. 11: force disable printing
340pub const UART_PRINT_CONTROL: EfuseField = EfuseField::new(0, 4, 134, 2);
341/// Represents whether ROM code is forced to send a resume command during SPI
342/// boot. 1: forced. 0:not forced
343pub const FORCE_SEND_RESUME: EfuseField = EfuseField::new(0, 4, 136, 1);
344/// Represents the version used by ESP-IDF anti-rollback feature
345pub const SECURE_VERSION: EfuseField = EfuseField::new(0, 4, 137, 16);
346/// Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure
347/// Boot is enabled. 1: disabled. 0: enabled
348pub const SECURE_BOOT_DISABLE_FAST_WAKE: EfuseField = EfuseField::new(0, 4, 153, 1);
349/// Represents whether the hysteresis function of corresponding PAD is enabled.
350/// 1: enabled. 0:disabled
351pub const HYS_EN_PAD: EfuseField = EfuseField::new(0, 4, 154, 1);
352/// Set the dcdc voltage default
353pub const DCDC_VSET: EfuseField = EfuseField::new(0, 4, 155, 5);
354/// TBD
355pub const PXA0_TIEH_SEL_0: EfuseField = EfuseField::new(0, 5, 160, 2);
356/// TBD
357pub const PXA0_TIEH_SEL_1: EfuseField = EfuseField::new(0, 5, 162, 2);
358/// TBD
359pub const PXA0_TIEH_SEL_2: EfuseField = EfuseField::new(0, 5, 164, 2);
360/// TBD
361pub const PXA0_TIEH_SEL_3: EfuseField = EfuseField::new(0, 5, 166, 2);
362/// TBD
363pub const KM_DISABLE_DEPLOY_MODE: EfuseField = EfuseField::new(0, 5, 168, 4);
364/// Represents the usb device single-end input low threshold; 0.8 V to 1.04 V
365/// with step of 80 mV
366pub const USB_DEVICE_DREFL: EfuseField = EfuseField::new(0, 5, 172, 2);
367/// Represents the usb otg11 single-end input low threshold; 0.8 V to 1.04 V
368/// with step of 80 mV
369pub const USB_OTG11_DREFL: EfuseField = EfuseField::new(0, 5, 174, 2);
370/// Reserved; it was created by set_missed_fields_in_regs func
371pub const RESERVE_0_176: EfuseField = EfuseField::new(0, 5, 176, 2);
372/// HP system power source select. 0:LDO. 1: DCDC
373pub const HP_PWR_SRC_SEL: EfuseField = EfuseField::new(0, 5, 178, 1);
374/// Select dcdc vset use efuse_dcdc_vset
375pub const DCDC_VSET_EN: EfuseField = EfuseField::new(0, 5, 179, 1);
376/// Set this bit to disable watch dog
377pub const DIS_WDT: EfuseField = EfuseField::new(0, 5, 180, 1);
378/// Set this bit to disable super-watchdog
379pub const DIS_SWD: EfuseField = EfuseField::new(0, 5, 181, 1);
380/// Reserved; it was created by set_missed_fields_in_regs func
381pub const RESERVE_0_182: EfuseField = EfuseField::new(0, 5, 182, 10);
382/// MAC address
383pub const MAC0: EfuseField = EfuseField::new(1, 0, 0, 32);
384/// MAC address
385pub const MAC1: EfuseField = EfuseField::new(1, 1, 32, 16);
386/// Stores the extended bits of MAC address
387pub const RESERVED_1_16: EfuseField = EfuseField::new(1, 1, 48, 16);
388/// Minor chip version
389pub const WAFER_VERSION_MINOR: EfuseField = EfuseField::new(1, 2, 64, 4);
390/// Major chip version (lower 2 bits)
391pub const WAFER_VERSION_MAJOR_LO: EfuseField = EfuseField::new(1, 2, 68, 2);
392/// Disables check of wafer version major
393pub const DISABLE_WAFER_VERSION_MAJOR: EfuseField = EfuseField::new(1, 2, 70, 1);
394/// Disables check of blk version major
395pub const DISABLE_BLK_VERSION_MAJOR: EfuseField = EfuseField::new(1, 2, 71, 1);
396/// BLK_VERSION_MINOR of BLOCK2
397pub const BLK_VERSION_MINOR: EfuseField = EfuseField::new(1, 2, 72, 3);
398/// BLK_VERSION_MAJOR of BLOCK2
399pub const BLK_VERSION_MAJOR: EfuseField = EfuseField::new(1, 2, 75, 2);
400/// PSRAM capacity
401pub const PSRAM_CAP: EfuseField = EfuseField::new(1, 2, 77, 3);
402/// Operating temperature of the ESP chip
403pub const TEMP: EfuseField = EfuseField::new(1, 2, 80, 2);
404/// PSRAM vendor
405pub const PSRAM_VENDOR: EfuseField = EfuseField::new(1, 2, 82, 2);
406/// Package version
407pub const PKG_VERSION: EfuseField = EfuseField::new(1, 2, 84, 3);
408/// Major chip version (MSB)
409pub const WAFER_VERSION_MAJOR_HI: EfuseField = EfuseField::new(1, 2, 87, 1);
410/// Output VO1 parameter
411pub const LDO_VO1_DREF: EfuseField = EfuseField::new(1, 2, 88, 4);
412/// Output VO2 parameter
413pub const LDO_VO2_DREF: EfuseField = EfuseField::new(1, 2, 92, 4);
414/// Output VO1 parameter
415pub const LDO_VO1_MUL: EfuseField = EfuseField::new(1, 3, 96, 3);
416/// Output VO2 parameter
417pub const LDO_VO2_MUL: EfuseField = EfuseField::new(1, 3, 99, 3);
418/// Output VO3 calibration parameter
419pub const LDO_VO3_K: EfuseField = EfuseField::new(1, 3, 102, 8);
420/// Output VO3 calibration parameter
421pub const LDO_VO3_VOS: EfuseField = EfuseField::new(1, 3, 110, 6);
422/// Output VO3 calibration parameter
423pub const LDO_VO3_C: EfuseField = EfuseField::new(1, 3, 116, 6);
424/// Output VO4 calibration parameter
425pub const LDO_VO4_K: EfuseField = EfuseField::new(1, 3, 122, 8);
426/// Output VO4 calibration parameter
427pub const LDO_VO4_VOS: EfuseField = EfuseField::new(1, 4, 130, 6);
428/// Output VO4 calibration parameter
429pub const LDO_VO4_C: EfuseField = EfuseField::new(1, 4, 136, 6);
430/// reserved
431pub const RESERVED_1_142: EfuseField = EfuseField::new(1, 4, 142, 2);
432/// Active HP DBIAS of fixed voltage
433pub const ACTIVE_HP_DBIAS: EfuseField = EfuseField::new(1, 4, 144, 4);
434/// Active LP DBIAS of fixed voltage
435pub const ACTIVE_LP_DBIAS: EfuseField = EfuseField::new(1, 4, 148, 4);
436/// LSLP HP DBIAS of fixed voltage
437pub const LSLP_HP_DBIAS: EfuseField = EfuseField::new(1, 4, 152, 4);
438/// DSLP BDG of fixed voltage
439pub const DSLP_DBG: EfuseField = EfuseField::new(1, 4, 156, 4);
440/// DSLP LP DBIAS of fixed voltage
441pub const DSLP_LP_DBIAS: EfuseField = EfuseField::new(1, 5, 160, 5);
442/// DBIAS gap between LP and DCDC
443pub const LP_DCDC_DBIAS_VOL_GAP: EfuseField = EfuseField::new(1, 5, 165, 5);
444/// reserved
445pub const RESERVED_1_170: EfuseField = EfuseField::new(1, 5, 170, 22);
446/// Optional unique 128-bit ID
447pub const OPTIONAL_UNIQUE_ID: EfuseField = EfuseField::new(2, 0, 0, 128);
448/// Average initcode of ADC1 atten0
449pub const ADC1_AVE_INITCODE_ATTEN0: EfuseField = EfuseField::new(2, 4, 128, 10);
450/// Average initcode of ADC1 atten1
451pub const ADC1_AVE_INITCODE_ATTEN1: EfuseField = EfuseField::new(2, 4, 138, 10);
452/// Average initcode of ADC1 atten2
453pub const ADC1_AVE_INITCODE_ATTEN2: EfuseField = EfuseField::new(2, 4, 148, 10);
454/// Average initcode of ADC1 atten3
455pub const ADC1_AVE_INITCODE_ATTEN3: EfuseField = EfuseField::new(2, 4, 158, 10);
456/// Average initcode of ADC2 atten0
457pub const ADC2_AVE_INITCODE_ATTEN0: EfuseField = EfuseField::new(2, 5, 168, 10);
458/// Average initcode of ADC2 atten1
459pub const ADC2_AVE_INITCODE_ATTEN1: EfuseField = EfuseField::new(2, 5, 178, 10);
460/// Average initcode of ADC2 atten2
461pub const ADC2_AVE_INITCODE_ATTEN2: EfuseField = EfuseField::new(2, 5, 188, 10);
462/// Average initcode of ADC2 atten3
463pub const ADC2_AVE_INITCODE_ATTEN3: EfuseField = EfuseField::new(2, 6, 198, 10);
464/// HI_DOUT of ADC1 atten0
465pub const ADC1_HI_DOUT_ATTEN0: EfuseField = EfuseField::new(2, 6, 208, 10);
466/// HI_DOUT of ADC1 atten1
467pub const ADC1_HI_DOUT_ATTEN1: EfuseField = EfuseField::new(2, 6, 218, 10);
468/// HI_DOUT of ADC1 atten2
469pub const ADC1_HI_DOUT_ATTEN2: EfuseField = EfuseField::new(2, 7, 228, 10);
470/// HI_DOUT of ADC1 atten3
471pub const ADC1_HI_DOUT_ATTEN3: EfuseField = EfuseField::new(2, 7, 238, 10);
472/// reserved
473pub const RESERVED_2_248: EfuseField = EfuseField::new(2, 7, 248, 8);
474/// User data
475pub const BLOCK_USR_DATA: EfuseField = EfuseField::new(3, 0, 0, 192);
476/// reserved
477pub const RESERVED_3_192: EfuseField = EfuseField::new(3, 6, 192, 8);
478/// Custom MAC
479pub const CUSTOM_MAC: EfuseField = EfuseField::new(3, 6, 200, 48);
480/// reserved
481pub const RESERVED_3_248: EfuseField = EfuseField::new(3, 7, 248, 8);
482/// Key0 or user data
483pub const BLOCK_KEY0: EfuseField = EfuseField::new(4, 0, 0, 256);
484/// Key1 or user data
485pub const BLOCK_KEY1: EfuseField = EfuseField::new(5, 0, 0, 256);
486/// Key2 or user data
487pub const BLOCK_KEY2: EfuseField = EfuseField::new(6, 0, 0, 256);
488/// Key3 or user data
489pub const BLOCK_KEY3: EfuseField = EfuseField::new(7, 0, 0, 256);
490/// Key4 or user data
491pub const BLOCK_KEY4: EfuseField = EfuseField::new(8, 0, 0, 256);
492/// Key5 or user data
493pub const BLOCK_KEY5: EfuseField = EfuseField::new(9, 0, 0, 256);
494/// HI_DOUT of ADC2 atten0
495pub const ADC2_HI_DOUT_ATTEN0: EfuseField = EfuseField::new(10, 0, 0, 10);
496/// HI_DOUT of ADC2 atten1
497pub const ADC2_HI_DOUT_ATTEN1: EfuseField = EfuseField::new(10, 0, 10, 10);
498/// HI_DOUT of ADC2 atten2
499pub const ADC2_HI_DOUT_ATTEN2: EfuseField = EfuseField::new(10, 0, 20, 10);
500/// HI_DOUT of ADC2 atten3
501pub const ADC2_HI_DOUT_ATTEN3: EfuseField = EfuseField::new(10, 0, 30, 10);
502/// Gap between ADC1_ch0 and average initcode
503pub const ADC1_CH0_ATTEN0_INITCODE_DIFF: EfuseField = EfuseField::new(10, 1, 40, 4);
504/// Gap between ADC1_ch1 and average initcode
505pub const ADC1_CH1_ATTEN0_INITCODE_DIFF: EfuseField = EfuseField::new(10, 1, 44, 4);
506/// Gap between ADC1_ch2 and average initcode
507pub const ADC1_CH2_ATTEN0_INITCODE_DIFF: EfuseField = EfuseField::new(10, 1, 48, 4);
508/// Gap between ADC1_ch3 and average initcode
509pub const ADC1_CH3_ATTEN0_INITCODE_DIFF: EfuseField = EfuseField::new(10, 1, 52, 4);
510/// Gap between ADC1_ch4 and average initcode
511pub const ADC1_CH4_ATTEN0_INITCODE_DIFF: EfuseField = EfuseField::new(10, 1, 56, 4);
512/// Gap between ADC1_ch5 and average initcode
513pub const ADC1_CH5_ATTEN0_INITCODE_DIFF: EfuseField = EfuseField::new(10, 1, 60, 4);
514/// Gap between ADC1_ch6 and average initcode
515pub const ADC1_CH6_ATTEN0_INITCODE_DIFF: EfuseField = EfuseField::new(10, 2, 64, 4);
516/// Gap between ADC1_ch7 and average initcode
517pub const ADC1_CH7_ATTEN0_INITCODE_DIFF: EfuseField = EfuseField::new(10, 2, 68, 4);
518/// Gap between ADC2_ch0 and average initcode
519pub const ADC2_CH0_ATTEN0_INITCODE_DIFF: EfuseField = EfuseField::new(10, 2, 72, 4);
520/// Gap between ADC2_ch1 and average initcode
521pub const ADC2_CH1_ATTEN0_INITCODE_DIFF: EfuseField = EfuseField::new(10, 2, 76, 4);
522/// Gap between ADC2_ch2 and average initcode
523pub const ADC2_CH2_ATTEN0_INITCODE_DIFF: EfuseField = EfuseField::new(10, 2, 80, 4);
524/// Gap between ADC2_ch3 and average initcode
525pub const ADC2_CH3_ATTEN0_INITCODE_DIFF: EfuseField = EfuseField::new(10, 2, 84, 4);
526/// Gap between ADC2_ch4 and average initcode
527pub const ADC2_CH4_ATTEN0_INITCODE_DIFF: EfuseField = EfuseField::new(10, 2, 88, 4);
528/// Gap between ADC2_ch5 and average initcode
529pub const ADC2_CH5_ATTEN0_INITCODE_DIFF: EfuseField = EfuseField::new(10, 2, 92, 4);
530/// Temperature calibration data
531pub const TEMPERATURE_SENSOR: EfuseField = EfuseField::new(10, 3, 96, 9);
532/// reserved
533pub const RESERVED_10_105: EfuseField = EfuseField::new(10, 3, 105, 23);
534/// Stores the $nth 32 bits of the 2nd part of system data
535pub const SYS_DATA_PART2_4: EfuseField = EfuseField::new(10, 4, 128, 32);
536/// Stores the $nth 32 bits of the 2nd part of system data
537pub const SYS_DATA_PART2_5: EfuseField = EfuseField::new(10, 5, 160, 32);
538/// Stores the $nth 32 bits of the 2nd part of system data
539pub const SYS_DATA_PART2_6: EfuseField = EfuseField::new(10, 6, 192, 32);
540/// Stores the $nth 32 bits of the 2nd part of system data
541pub const SYS_DATA_PART2_7: EfuseField = EfuseField::new(10, 7, 224, 32);
espflash/target/efuse/esp32p4.rs

espflash/target/efuse/
esp32p4.rs
