esp8266/spi0/
spi_addr.rs

1#[doc = "Register `SPI_ADDR` reader"]
2pub struct R(crate::R<SPI_ADDR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SPI_ADDR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SPI_ADDR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SPI_ADDR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SPI_ADDR` writer"]
17pub struct W(crate::W<SPI_ADDR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SPI_ADDR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SPI_ADDR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SPI_ADDR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `iodata_start_addr` reader - In the master mode, it is the value of address in \"address\" phase."]
38pub struct IODATA_START_ADDR_R(crate::FieldReader<u32, u32>);
39impl IODATA_START_ADDR_R {
40    #[inline(always)]
41    pub(crate) fn new(bits: u32) -> Self {
42        IODATA_START_ADDR_R(crate::FieldReader::new(bits))
43    }
44}
45impl core::ops::Deref for IODATA_START_ADDR_R {
46    type Target = crate::FieldReader<u32, u32>;
47    #[inline(always)]
48    fn deref(&self) -> &Self::Target {
49        &self.0
50    }
51}
52#[doc = "Field `iodata_start_addr` writer - In the master mode, it is the value of address in \"address\" phase."]
53pub struct IODATA_START_ADDR_W<'a> {
54    w: &'a mut W,
55}
56impl<'a> IODATA_START_ADDR_W<'a> {
57    #[doc = r"Writes raw bits to the field"]
58    #[inline(always)]
59    pub unsafe fn bits(self, value: u32) -> &'a mut W {
60        self.w.bits = value;
61        self.w
62    }
63}
64#[doc = "Field `address` reader - "]
65pub struct ADDRESS_R(crate::FieldReader<u32, u32>);
66impl ADDRESS_R {
67    #[inline(always)]
68    pub(crate) fn new(bits: u32) -> Self {
69        ADDRESS_R(crate::FieldReader::new(bits))
70    }
71}
72impl core::ops::Deref for ADDRESS_R {
73    type Target = crate::FieldReader<u32, u32>;
74    #[inline(always)]
75    fn deref(&self) -> &Self::Target {
76        &self.0
77    }
78}
79#[doc = "Field `address` writer - "]
80pub struct ADDRESS_W<'a> {
81    w: &'a mut W,
82}
83impl<'a> ADDRESS_W<'a> {
84    #[doc = r"Writes raw bits to the field"]
85    #[inline(always)]
86    pub unsafe fn bits(self, value: u32) -> &'a mut W {
87        self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff);
88        self.w
89    }
90}
91#[doc = "Field `size` reader - "]
92pub struct SIZE_R(crate::FieldReader<u8, u8>);
93impl SIZE_R {
94    #[inline(always)]
95    pub(crate) fn new(bits: u8) -> Self {
96        SIZE_R(crate::FieldReader::new(bits))
97    }
98}
99impl core::ops::Deref for SIZE_R {
100    type Target = crate::FieldReader<u8, u8>;
101    #[inline(always)]
102    fn deref(&self) -> &Self::Target {
103        &self.0
104    }
105}
106#[doc = "Field `size` writer - "]
107pub struct SIZE_W<'a> {
108    w: &'a mut W,
109}
110impl<'a> SIZE_W<'a> {
111    #[doc = r"Writes raw bits to the field"]
112    #[inline(always)]
113    pub unsafe fn bits(self, value: u8) -> &'a mut W {
114        self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24);
115        self.w
116    }
117}
118impl R {
119    #[doc = "Bits 0:31 - In the master mode, it is the value of address in \"address\" phase."]
120    #[inline(always)]
121    pub fn iodata_start_addr(&self) -> IODATA_START_ADDR_R {
122        IODATA_START_ADDR_R::new(self.bits)
123    }
124    #[doc = "Bits 0:23"]
125    #[inline(always)]
126    pub fn address(&self) -> ADDRESS_R {
127        ADDRESS_R::new((self.bits & 0x00ff_ffff) as u32)
128    }
129    #[doc = "Bits 24:31"]
130    #[inline(always)]
131    pub fn size(&self) -> SIZE_R {
132        SIZE_R::new(((self.bits >> 24) & 0xff) as u8)
133    }
134}
135impl W {
136    #[doc = "Bits 0:31 - In the master mode, it is the value of address in \"address\" phase."]
137    #[inline(always)]
138    pub fn iodata_start_addr(&mut self) -> IODATA_START_ADDR_W {
139        IODATA_START_ADDR_W { w: self }
140    }
141    #[doc = "Bits 0:23"]
142    #[inline(always)]
143    pub fn address(&mut self) -> ADDRESS_W {
144        ADDRESS_W { w: self }
145    }
146    #[doc = "Bits 24:31"]
147    #[inline(always)]
148    pub fn size(&mut self) -> SIZE_W {
149        SIZE_W { w: self }
150    }
151    #[doc = "Writes raw bits to the register."]
152    #[inline(always)]
153    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
154        self.0.bits(bits);
155        self
156    }
157}
158#[doc = "In the master mode, it is the value of address in \"address\" phase.\n\nThis register you can [`read`]
159(crate::generic::Reg::read), [`write_with_zero`]
160(crate::generic::Reg::write_with_zero), [`reset`]
161(crate::generic::Reg::reset), [`write`]
162(crate::generic::Reg::write), [`modify`]
163(crate::generic::Reg::modify). See [API]
164(https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [spi_addr]
165(index.html) module"]
166pub struct SPI_ADDR_SPEC;
167impl crate::RegisterSpec for SPI_ADDR_SPEC {
168    type Ux = u32;
169}
170#[doc = "`read()` method returns [spi_addr::R]
171(R) reader structure"]
172impl crate::Readable for SPI_ADDR_SPEC {
173    type Reader = R;
174}
175#[doc = "`write(|w| ..)` method takes [spi_addr::W]
176(W) writer structure"]
177impl crate::Writable for SPI_ADDR_SPEC {
178    type Writer = W;
179}
180#[doc = "`reset()` method sets SPI_ADDR to value 0"]
181impl crate::Resettable for SPI_ADDR_SPEC {
182    #[inline(always)]
183    fn reset_value() -> Self::Ux {
184        0
185    }
186}
esp8266/spi0/spi_addr.rs

esp8266/spi0/
spi_addr.rs
