esp8266/gpio/
gpio_rtc_calib_sync.rs

1#[doc = "Register `GPIO_RTC_CALIB_SYNC` reader"]
2pub struct R(crate::R<GPIO_RTC_CALIB_SYNC_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<GPIO_RTC_CALIB_SYNC_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<GPIO_RTC_CALIB_SYNC_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<GPIO_RTC_CALIB_SYNC_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `GPIO_RTC_CALIB_SYNC` writer"]
17pub struct W(crate::W<GPIO_RTC_CALIB_SYNC_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<GPIO_RTC_CALIB_SYNC_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<GPIO_RTC_CALIB_SYNC_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<GPIO_RTC_CALIB_SYNC_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `RTC_CALIB_START` reader - Positvie edge of this bit will trigger the RTC-clock-calibration process."]
38pub struct RTC_CALIB_START_R(crate::FieldReader<bool, bool>);
39impl RTC_CALIB_START_R {
40    #[inline(always)]
41    pub(crate) fn new(bits: bool) -> Self {
42        RTC_CALIB_START_R(crate::FieldReader::new(bits))
43    }
44}
45impl core::ops::Deref for RTC_CALIB_START_R {
46    type Target = crate::FieldReader<bool, bool>;
47    #[inline(always)]
48    fn deref(&self) -> &Self::Target {
49        &self.0
50    }
51}
52#[doc = "Field `RTC_CALIB_START` writer - Positvie edge of this bit will trigger the RTC-clock-calibration process."]
53pub struct RTC_CALIB_START_W<'a> {
54    w: &'a mut W,
55}
56impl<'a> RTC_CALIB_START_W<'a> {
57    #[doc = r"Sets the field bit"]
58    #[inline(always)]
59    pub fn set_bit(self) -> &'a mut W {
60        self.bit(true)
61    }
62    #[doc = r"Clears the field bit"]
63    #[inline(always)]
64    pub fn clear_bit(self) -> &'a mut W {
65        self.bit(false)
66    }
67    #[doc = r"Writes raw bits to the field"]
68    #[inline(always)]
69    pub fn bit(self, value: bool) -> &'a mut W {
70        self.w.bits = (self.w.bits & !(1 << 31)) | ((value as u32 & 1) << 31);
71        self.w
72    }
73}
74#[doc = "Field `RTC_PERIOD_NUM` reader - The cycle number of RTC-clock during RTC-clock-calibration"]
75pub struct RTC_PERIOD_NUM_R(crate::FieldReader<u16, u16>);
76impl RTC_PERIOD_NUM_R {
77    #[inline(always)]
78    pub(crate) fn new(bits: u16) -> Self {
79        RTC_PERIOD_NUM_R(crate::FieldReader::new(bits))
80    }
81}
82impl core::ops::Deref for RTC_PERIOD_NUM_R {
83    type Target = crate::FieldReader<u16, u16>;
84    #[inline(always)]
85    fn deref(&self) -> &Self::Target {
86        &self.0
87    }
88}
89#[doc = "Field `RTC_PERIOD_NUM` writer - The cycle number of RTC-clock during RTC-clock-calibration"]
90pub struct RTC_PERIOD_NUM_W<'a> {
91    w: &'a mut W,
92}
93impl<'a> RTC_PERIOD_NUM_W<'a> {
94    #[doc = r"Writes raw bits to the field"]
95    #[inline(always)]
96    pub unsafe fn bits(self, value: u16) -> &'a mut W {
97        self.w.bits = (self.w.bits & !0x03ff) | (value as u32 & 0x03ff);
98        self.w
99    }
100}
101impl R {
102    #[doc = "Bit 31 - Positvie edge of this bit will trigger the RTC-clock-calibration process."]
103    #[inline(always)]
104    pub fn rtc_calib_start(&self) -> RTC_CALIB_START_R {
105        RTC_CALIB_START_R::new(((self.bits >> 31) & 1) != 0)
106    }
107    #[doc = "Bits 0:9 - The cycle number of RTC-clock during RTC-clock-calibration"]
108    #[inline(always)]
109    pub fn rtc_period_num(&self) -> RTC_PERIOD_NUM_R {
110        RTC_PERIOD_NUM_R::new((self.bits & 0x03ff) as u16)
111    }
112}
113impl W {
114    #[doc = "Bit 31 - Positvie edge of this bit will trigger the RTC-clock-calibration process."]
115    #[inline(always)]
116    pub fn rtc_calib_start(&mut self) -> RTC_CALIB_START_W {
117        RTC_CALIB_START_W { w: self }
118    }
119    #[doc = "Bits 0:9 - The cycle number of RTC-clock during RTC-clock-calibration"]
120    #[inline(always)]
121    pub fn rtc_period_num(&mut self) -> RTC_PERIOD_NUM_W {
122        RTC_PERIOD_NUM_W { w: self }
123    }
124    #[doc = "Writes raw bits to the register."]
125    #[inline(always)]
126    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
127        self.0.bits(bits);
128        self
129    }
130}
131#[doc = "Positvie edge of this bit will trigger the RTC-clock-calibration process.\n\nThis register you can [`read`]
132(crate::generic::Reg::read), [`write_with_zero`]
133(crate::generic::Reg::write_with_zero), [`reset`]
134(crate::generic::Reg::reset), [`write`]
135(crate::generic::Reg::write), [`modify`]
136(crate::generic::Reg::modify). See [API]
137(https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpio_rtc_calib_sync]
138(index.html) module"]
139pub struct GPIO_RTC_CALIB_SYNC_SPEC;
140impl crate::RegisterSpec for GPIO_RTC_CALIB_SYNC_SPEC {
141    type Ux = u32;
142}
143#[doc = "`read()` method returns [gpio_rtc_calib_sync::R]
144(R) reader structure"]
145impl crate::Readable for GPIO_RTC_CALIB_SYNC_SPEC {
146    type Reader = R;
147}
148#[doc = "`write(|w| ..)` method takes [gpio_rtc_calib_sync::W]
149(W) writer structure"]
150impl crate::Writable for GPIO_RTC_CALIB_SYNC_SPEC {
151    type Writer = W;
152}
153#[doc = "`reset()` method sets GPIO_RTC_CALIB_SYNC to value 0"]
154impl crate::Resettable for GPIO_RTC_CALIB_SYNC_SPEC {
155    #[inline(always)]
156    fn reset_value() -> Self::Ux {
157        0
158    }
159}
esp8266/gpio/gpio_rtc_calib_sync.rs

esp8266/gpio/
gpio_rtc_calib_sync.rs
