1#[doc = "Register `SPI_PIN` reader"]
2pub struct R(crate::R<SPI_PIN_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<SPI_PIN_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<SPI_PIN_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<SPI_PIN_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `SPI_PIN` writer"]
17pub struct W(crate::W<SPI_PIN_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<SPI_PIN_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<SPI_PIN_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<SPI_PIN_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `spi_cs2_dis` reader - 1: disable CS2; 0: spi_cs signal is from/to CS2 pin"]
38pub struct SPI_CS2_DIS_R(crate::FieldReader<bool, bool>);
39impl SPI_CS2_DIS_R {
40 #[inline(always)]
41 pub(crate) fn new(bits: bool) -> Self {
42 SPI_CS2_DIS_R(crate::FieldReader::new(bits))
43 }
44}
45impl core::ops::Deref for SPI_CS2_DIS_R {
46 type Target = crate::FieldReader<bool, bool>;
47 #[inline(always)]
48 fn deref(&self) -> &Self::Target {
49 &self.0
50 }
51}
52#[doc = "Field `spi_cs2_dis` writer - 1: disable CS2; 0: spi_cs signal is from/to CS2 pin"]
53pub struct SPI_CS2_DIS_W<'a> {
54 w: &'a mut W,
55}
56impl<'a> SPI_CS2_DIS_W<'a> {
57 #[doc = r"Sets the field bit"]
58 #[inline(always)]
59 pub fn set_bit(self) -> &'a mut W {
60 self.bit(true)
61 }
62 #[doc = r"Clears the field bit"]
63 #[inline(always)]
64 pub fn clear_bit(self) -> &'a mut W {
65 self.bit(false)
66 }
67 #[doc = r"Writes raw bits to the field"]
68 #[inline(always)]
69 pub fn bit(self, value: bool) -> &'a mut W {
70 self.w.bits = (self.w.bits & !(1 << 2)) | ((value as u32 & 1) << 2);
71 self.w
72 }
73}
74#[doc = "Field `spi_cs1_dis` reader - 1: disable CS1; 0: spi_cs signal is from/to CS1 pin"]
75pub struct SPI_CS1_DIS_R(crate::FieldReader<bool, bool>);
76impl SPI_CS1_DIS_R {
77 #[inline(always)]
78 pub(crate) fn new(bits: bool) -> Self {
79 SPI_CS1_DIS_R(crate::FieldReader::new(bits))
80 }
81}
82impl core::ops::Deref for SPI_CS1_DIS_R {
83 type Target = crate::FieldReader<bool, bool>;
84 #[inline(always)]
85 fn deref(&self) -> &Self::Target {
86 &self.0
87 }
88}
89#[doc = "Field `spi_cs1_dis` writer - 1: disable CS1; 0: spi_cs signal is from/to CS1 pin"]
90pub struct SPI_CS1_DIS_W<'a> {
91 w: &'a mut W,
92}
93impl<'a> SPI_CS1_DIS_W<'a> {
94 #[doc = r"Sets the field bit"]
95 #[inline(always)]
96 pub fn set_bit(self) -> &'a mut W {
97 self.bit(true)
98 }
99 #[doc = r"Clears the field bit"]
100 #[inline(always)]
101 pub fn clear_bit(self) -> &'a mut W {
102 self.bit(false)
103 }
104 #[doc = r"Writes raw bits to the field"]
105 #[inline(always)]
106 pub fn bit(self, value: bool) -> &'a mut W {
107 self.w.bits = (self.w.bits & !(1 << 1)) | ((value as u32 & 1) << 1);
108 self.w
109 }
110}
111#[doc = "Field `spi_cs0_dis` reader - 1: disable CS0; 0: spi_cs signal is from/to CS0 pin"]
112pub struct SPI_CS0_DIS_R(crate::FieldReader<bool, bool>);
113impl SPI_CS0_DIS_R {
114 #[inline(always)]
115 pub(crate) fn new(bits: bool) -> Self {
116 SPI_CS0_DIS_R(crate::FieldReader::new(bits))
117 }
118}
119impl core::ops::Deref for SPI_CS0_DIS_R {
120 type Target = crate::FieldReader<bool, bool>;
121 #[inline(always)]
122 fn deref(&self) -> &Self::Target {
123 &self.0
124 }
125}
126#[doc = "Field `spi_cs0_dis` writer - 1: disable CS0; 0: spi_cs signal is from/to CS0 pin"]
127pub struct SPI_CS0_DIS_W<'a> {
128 w: &'a mut W,
129}
130impl<'a> SPI_CS0_DIS_W<'a> {
131 #[doc = r"Sets the field bit"]
132 #[inline(always)]
133 pub fn set_bit(self) -> &'a mut W {
134 self.bit(true)
135 }
136 #[doc = r"Clears the field bit"]
137 #[inline(always)]
138 pub fn clear_bit(self) -> &'a mut W {
139 self.bit(false)
140 }
141 #[doc = r"Writes raw bits to the field"]
142 #[inline(always)]
143 pub fn bit(self, value: bool) -> &'a mut W {
144 self.w.bits = (self.w.bits & !1) | (value as u32 & 1);
145 self.w
146 }
147}
148#[doc = "Field `spi_idle_edge` reader - In the master mode, 1: high when idle; 0: low when idle"]
149pub struct SPI_IDLE_EDGE_R(crate::FieldReader<bool, bool>);
150impl SPI_IDLE_EDGE_R {
151 #[inline(always)]
152 pub(crate) fn new(bits: bool) -> Self {
153 SPI_IDLE_EDGE_R(crate::FieldReader::new(bits))
154 }
155}
156impl core::ops::Deref for SPI_IDLE_EDGE_R {
157 type Target = crate::FieldReader<bool, bool>;
158 #[inline(always)]
159 fn deref(&self) -> &Self::Target {
160 &self.0
161 }
162}
163#[doc = "Field `spi_idle_edge` writer - In the master mode, 1: high when idle; 0: low when idle"]
164pub struct SPI_IDLE_EDGE_W<'a> {
165 w: &'a mut W,
166}
167impl<'a> SPI_IDLE_EDGE_W<'a> {
168 #[doc = r"Sets the field bit"]
169 #[inline(always)]
170 pub fn set_bit(self) -> &'a mut W {
171 self.bit(true)
172 }
173 #[doc = r"Clears the field bit"]
174 #[inline(always)]
175 pub fn clear_bit(self) -> &'a mut W {
176 self.bit(false)
177 }
178 #[doc = r"Writes raw bits to the field"]
179 #[inline(always)]
180 pub fn bit(self, value: bool) -> &'a mut W {
181 self.w.bits = (self.w.bits & !(1 << 29)) | ((value as u32 & 1) << 29);
182 self.w
183 }
184}
185impl R {
186 #[doc = "Bit 2 - 1: disable CS2; 0: spi_cs signal is from/to CS2 pin"]
187 #[inline(always)]
188 pub fn spi_cs2_dis(&self) -> SPI_CS2_DIS_R {
189 SPI_CS2_DIS_R::new(((self.bits >> 2) & 1) != 0)
190 }
191 #[doc = "Bit 1 - 1: disable CS1; 0: spi_cs signal is from/to CS1 pin"]
192 #[inline(always)]
193 pub fn spi_cs1_dis(&self) -> SPI_CS1_DIS_R {
194 SPI_CS1_DIS_R::new(((self.bits >> 1) & 1) != 0)
195 }
196 #[doc = "Bit 0 - 1: disable CS0; 0: spi_cs signal is from/to CS0 pin"]
197 #[inline(always)]
198 pub fn spi_cs0_dis(&self) -> SPI_CS0_DIS_R {
199 SPI_CS0_DIS_R::new((self.bits & 1) != 0)
200 }
201 #[doc = "Bit 29 - In the master mode, 1: high when idle; 0: low when idle"]
202 #[inline(always)]
203 pub fn spi_idle_edge(&self) -> SPI_IDLE_EDGE_R {
204 SPI_IDLE_EDGE_R::new(((self.bits >> 29) & 1) != 0)
205 }
206}
207impl W {
208 #[doc = "Bit 2 - 1: disable CS2; 0: spi_cs signal is from/to CS2 pin"]
209 #[inline(always)]
210 pub fn spi_cs2_dis(&mut self) -> SPI_CS2_DIS_W {
211 SPI_CS2_DIS_W { w: self }
212 }
213 #[doc = "Bit 1 - 1: disable CS1; 0: spi_cs signal is from/to CS1 pin"]
214 #[inline(always)]
215 pub fn spi_cs1_dis(&mut self) -> SPI_CS1_DIS_W {
216 SPI_CS1_DIS_W { w: self }
217 }
218 #[doc = "Bit 0 - 1: disable CS0; 0: spi_cs signal is from/to CS0 pin"]
219 #[inline(always)]
220 pub fn spi_cs0_dis(&mut self) -> SPI_CS0_DIS_W {
221 SPI_CS0_DIS_W { w: self }
222 }
223 #[doc = "Bit 29 - In the master mode, 1: high when idle; 0: low when idle"]
224 #[inline(always)]
225 pub fn spi_idle_edge(&mut self) -> SPI_IDLE_EDGE_W {
226 SPI_IDLE_EDGE_W { w: self }
227 }
228 #[doc = "Writes raw bits to the register."]
229 #[inline(always)]
230 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
231 self.0.bits(bits);
232 self
233 }
234}
235#[doc = "1: disable CS2; 0: spi_cs signal is from/to CS2 pin\n\nThis register you can [`read`]
236(crate::generic::Reg::read), [`write_with_zero`]
237(crate::generic::Reg::write_with_zero), [`reset`]
238(crate::generic::Reg::reset), [`write`]
239(crate::generic::Reg::write), [`modify`]
240(crate::generic::Reg::modify). See [API]
241(https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [spi_pin]
242(index.html) module"]
243pub struct SPI_PIN_SPEC;
244impl crate::RegisterSpec for SPI_PIN_SPEC {
245 type Ux = u32;
246}
247#[doc = "`read()` method returns [spi_pin::R]
248(R) reader structure"]
249impl crate::Readable for SPI_PIN_SPEC {
250 type Reader = R;
251}
252#[doc = "`write(|w| ..)` method takes [spi_pin::W]
253(W) writer structure"]
254impl crate::Writable for SPI_PIN_SPEC {
255 type Writer = W;
256}
257#[doc = "`reset()` method sets SPI_PIN to value 0"]
258impl crate::Resettable for SPI_PIN_SPEC {
259 #[inline(always)]
260 fn reset_value() -> Self::Ux {
261 0
262 }
263}