Module spi_ctrl2 

spi_cs signal is delayed by 80MHz clock cycles

Structs

R

Register SPI_CTRL2 reader

SPI_CS_DELAY_MODE_R

Field spi_cs_delay_mode reader - spi_cs signal is delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle

SPI_CS_DELAY_MODE_W

Field spi_cs_delay_mode writer - spi_cs signal is delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle

SPI_CS_DELAY_NUM_R

Field spi_cs_delay_num reader - spi_cs signal is delayed by 80MHz clock cycles

SPI_CS_DELAY_NUM_W

Field spi_cs_delay_num writer - spi_cs signal is delayed by 80MHz clock cycles

SPI_CTRL2_SPEC

spi_cs signal is delayed by 80MHz clock cycles

SPI_MISO_DELAY_MODE_R

Field spi_miso_delay_mode reader - MISO signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle

SPI_MISO_DELAY_MODE_W

Field spi_miso_delay_mode writer - MISO signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle

SPI_MISO_DELAY_NUM_R

Field spi_miso_delay_num reader - MISO signals are delayed by 80MHz clock cycles

SPI_MISO_DELAY_NUM_W

Field spi_miso_delay_num writer - MISO signals are delayed by 80MHz clock cycles

SPI_MOSI_DELAY_MODE_R

Field spi_mosi_delay_mode reader - MOSI signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle

SPI_MOSI_DELAY_MODE_W

Field spi_mosi_delay_mode writer - MOSI signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle

SPI_MOSI_DELAY_NUM_R

Field spi_mosi_delay_num reader - MOSI signals are delayed by 80MHz clock cycles

SPI_MOSI_DELAY_NUM_W

Field spi_mosi_delay_num writer - MOSI signals are delayed by 80MHz clock cycles

W

Register SPI_CTRL2 writer