Module spi_clock 

In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock.

Structs

R

Register SPI_CLOCK reader

SPI_CLKCNT_H_R

Field spi_clkcnt_H reader - In the master mode, it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode, it must be 0.

SPI_CLKCNT_H_W

Field spi_clkcnt_H writer - In the master mode, it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode, it must be 0.

SPI_CLKCNT_L_R

Field spi_clkcnt_L reader - In the master mode, it must be eqaul to spi_clkcnt_N. In the slave mode, it must be 0.

SPI_CLKCNT_L_W

Field spi_clkcnt_L writer - In the master mode, it must be eqaul to spi_clkcnt_N. In the slave mode, it must be 0.

SPI_CLKCNT_N_R

Field spi_clkcnt_N reader - In the master mode, it is the divider of spi_clk. So spi_clk frequency is 80MHz/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)

SPI_CLKCNT_N_W

Field spi_clkcnt_N writer - In the master mode, it is the divider of spi_clk. So spi_clk frequency is 80MHz/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)

SPI_CLKDIV_PRE_R

Field spi_clkdiv_pre reader - In the master mode, it is pre-divider of spi_clk.

SPI_CLKDIV_PRE_W

Field spi_clkdiv_pre writer - In the master mode, it is pre-divider of spi_clk.

SPI_CLK_EQU_SYSCLK_R

Field spi_clk_equ_sysclk reader - In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock.

SPI_CLK_EQU_SYSCLK_W

Field spi_clk_equ_sysclk writer - In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock.

SPI_CLOCK_SPEC

In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock.

W

Register SPI_CLOCK writer