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#[doc = "Reader of register SLC_AHB_TEST"] pub struct R(crate::R<SLC_AHB_TEST_SPEC>); impl core::ops::Deref for R { type Target = crate::R<SLC_AHB_TEST_SPEC>; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::convert::From<crate::R<SLC_AHB_TEST_SPEC>> for R { fn from(reader: crate::R<SLC_AHB_TEST_SPEC>) -> Self { R(reader) } } #[doc = "Writer for register SLC_AHB_TEST"] pub struct W(crate::W<SLC_AHB_TEST_SPEC>); impl core::ops::Deref for W { type Target = crate::W<SLC_AHB_TEST_SPEC>; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl core::convert::From<crate::W<SLC_AHB_TEST_SPEC>> for W { fn from(writer: crate::W<SLC_AHB_TEST_SPEC>) -> Self { W(writer) } } #[doc = "Reader of field `SLC_AHB_TESTADDR`"] pub struct SLC_AHB_TESTADDR_R(crate::FieldReader<u8, u8>); impl SLC_AHB_TESTADDR_R { pub(crate) fn new(bits: u8) -> Self { SLC_AHB_TESTADDR_R(crate::FieldReader::new(bits)) } } impl core::ops::Deref for SLC_AHB_TESTADDR_R { type Target = crate::FieldReader<u8, u8>; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } #[doc = "Write proxy for field `SLC_AHB_TESTADDR`"] pub struct SLC_AHB_TESTADDR_W<'a> { w: &'a mut W, } impl<'a> SLC_AHB_TESTADDR_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u32) & 0x03) << 4); self.w } } #[doc = "Reader of field `SLC_AHB_TESTMODE`"] pub struct SLC_AHB_TESTMODE_R(crate::FieldReader<u8, u8>); impl SLC_AHB_TESTMODE_R { pub(crate) fn new(bits: u8) -> Self { SLC_AHB_TESTMODE_R(crate::FieldReader::new(bits)) } } impl core::ops::Deref for SLC_AHB_TESTMODE_R { type Target = crate::FieldReader<u8, u8>; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } #[doc = "Write proxy for field `SLC_AHB_TESTMODE`"] pub struct SLC_AHB_TESTMODE_W<'a> { w: &'a mut W, } impl<'a> SLC_AHB_TESTMODE_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07); self.w } } impl R { #[doc = "Bits 4:5"] #[inline(always)] pub fn slc_ahb_testaddr(&self) -> SLC_AHB_TESTADDR_R { SLC_AHB_TESTADDR_R::new(((self.bits >> 4) & 0x03) as u8) } #[doc = "Bits 0:2"] #[inline(always)] pub fn slc_ahb_testmode(&self) -> SLC_AHB_TESTMODE_R { SLC_AHB_TESTMODE_R::new((self.bits & 0x07) as u8) } } impl W { #[doc = "Bits 4:5"] #[inline(always)] pub fn slc_ahb_testaddr(&mut self) -> SLC_AHB_TESTADDR_W { SLC_AHB_TESTADDR_W { w: self } } #[doc = "Bits 0:2"] #[inline(always)] pub fn slc_ahb_testmode(&mut self) -> SLC_AHB_TESTMODE_W { SLC_AHB_TESTMODE_W { w: self } } #[doc = "Writes raw bits to the register."] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "SLC_AHB_TEST\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [slc_ahb_test](index.html) module"] pub struct SLC_AHB_TEST_SPEC; impl crate::RegisterSpec for SLC_AHB_TEST_SPEC { type Ux = u32; } #[doc = "`read()` method returns [slc_ahb_test::R](R) reader structure"] impl crate::Readable for SLC_AHB_TEST_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [slc_ahb_test::W](W) writer structure"] impl crate::Writable for SLC_AHB_TEST_SPEC { type Writer = W; } #[doc = "`reset()` method sets SLC_AHB_TEST to value 0"] impl crate::Resettable for SLC_AHB_TEST_SPEC { #[inline(always)] fn reset_value() -> Self::Ux { 0 } }