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#[doc = "Reader of register SPI_CTRL2"]
pub type R = crate::R<u32, super::SPI_CTRL2>;
#[doc = "Writer for register SPI_CTRL2"]
pub type W = crate::W<u32, super::SPI_CTRL2>;
#[doc = "Register SPI_CTRL2 `reset()`'s with value 0"]
impl crate::ResetValue for super::SPI_CTRL2 {
    type Type = u32;
    #[inline(always)]
    fn reset_value() -> Self::Type {
        0
    }
}
#[doc = "Reader of field `spi_cs_delay_num`"]
pub type SPI_CS_DELAY_NUM_R = crate::R<u8, u8>;
#[doc = "Write proxy for field `spi_cs_delay_num`"]
pub struct SPI_CS_DELAY_NUM_W<'a> {
    w: &'a mut W,
}
impl<'a> SPI_CS_DELAY_NUM_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x0f << 28)) | (((value as u32) & 0x0f) << 28);
        self.w
    }
}
#[doc = "Reader of field `spi_cs_delay_mode`"]
pub type SPI_CS_DELAY_MODE_R = crate::R<u8, u8>;
#[doc = "Write proxy for field `spi_cs_delay_mode`"]
pub struct SPI_CS_DELAY_MODE_W<'a> {
    w: &'a mut W,
}
impl<'a> SPI_CS_DELAY_MODE_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x03 << 26)) | (((value as u32) & 0x03) << 26);
        self.w
    }
}
#[doc = "Reader of field `spi_mosi_delay_num`"]
pub type SPI_MOSI_DELAY_NUM_R = crate::R<u8, u8>;
#[doc = "Write proxy for field `spi_mosi_delay_num`"]
pub struct SPI_MOSI_DELAY_NUM_W<'a> {
    w: &'a mut W,
}
impl<'a> SPI_MOSI_DELAY_NUM_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x07 << 23)) | (((value as u32) & 0x07) << 23);
        self.w
    }
}
#[doc = "Reader of field `spi_mosi_delay_mode`"]
pub type SPI_MOSI_DELAY_MODE_R = crate::R<u8, u8>;
#[doc = "Write proxy for field `spi_mosi_delay_mode`"]
pub struct SPI_MOSI_DELAY_MODE_W<'a> {
    w: &'a mut W,
}
impl<'a> SPI_MOSI_DELAY_MODE_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x03 << 21)) | (((value as u32) & 0x03) << 21);
        self.w
    }
}
#[doc = "Reader of field `spi_miso_delay_num`"]
pub type SPI_MISO_DELAY_NUM_R = crate::R<u8, u8>;
#[doc = "Write proxy for field `spi_miso_delay_num`"]
pub struct SPI_MISO_DELAY_NUM_W<'a> {
    w: &'a mut W,
}
impl<'a> SPI_MISO_DELAY_NUM_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x07 << 18)) | (((value as u32) & 0x07) << 18);
        self.w
    }
}
#[doc = "Reader of field `spi_miso_delay_mode`"]
pub type SPI_MISO_DELAY_MODE_R = crate::R<u8, u8>;
#[doc = "Write proxy for field `spi_miso_delay_mode`"]
pub struct SPI_MISO_DELAY_MODE_W<'a> {
    w: &'a mut W,
}
impl<'a> SPI_MISO_DELAY_MODE_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x03 << 16)) | (((value as u32) & 0x03) << 16);
        self.w
    }
}
impl R {
    #[doc = "Bits 28:31 - spi_cs signal is delayed by 80MHz clock cycles"]
    #[inline(always)]
    pub fn spi_cs_delay_num(&self) -> SPI_CS_DELAY_NUM_R {
        SPI_CS_DELAY_NUM_R::new(((self.bits >> 28) & 0x0f) as u8)
    }
    #[doc = "Bits 26:27 - spi_cs signal is delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle"]
    #[inline(always)]
    pub fn spi_cs_delay_mode(&self) -> SPI_CS_DELAY_MODE_R {
        SPI_CS_DELAY_MODE_R::new(((self.bits >> 26) & 0x03) as u8)
    }
    #[doc = "Bits 23:25 - MOSI signals are delayed by 80MHz clock cycles"]
    #[inline(always)]
    pub fn spi_mosi_delay_num(&self) -> SPI_MOSI_DELAY_NUM_R {
        SPI_MOSI_DELAY_NUM_R::new(((self.bits >> 23) & 0x07) as u8)
    }
    #[doc = "Bits 21:22 - MOSI signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle"]
    #[inline(always)]
    pub fn spi_mosi_delay_mode(&self) -> SPI_MOSI_DELAY_MODE_R {
        SPI_MOSI_DELAY_MODE_R::new(((self.bits >> 21) & 0x03) as u8)
    }
    #[doc = "Bits 18:20 - MISO signals are delayed by 80MHz clock cycles"]
    #[inline(always)]
    pub fn spi_miso_delay_num(&self) -> SPI_MISO_DELAY_NUM_R {
        SPI_MISO_DELAY_NUM_R::new(((self.bits >> 18) & 0x07) as u8)
    }
    #[doc = "Bits 16:17 - MISO signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle"]
    #[inline(always)]
    pub fn spi_miso_delay_mode(&self) -> SPI_MISO_DELAY_MODE_R {
        SPI_MISO_DELAY_MODE_R::new(((self.bits >> 16) & 0x03) as u8)
    }
}
impl W {
    #[doc = "Bits 28:31 - spi_cs signal is delayed by 80MHz clock cycles"]
    #[inline(always)]
    pub fn spi_cs_delay_num(&mut self) -> SPI_CS_DELAY_NUM_W {
        SPI_CS_DELAY_NUM_W { w: self }
    }
    #[doc = "Bits 26:27 - spi_cs signal is delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle"]
    #[inline(always)]
    pub fn spi_cs_delay_mode(&mut self) -> SPI_CS_DELAY_MODE_W {
        SPI_CS_DELAY_MODE_W { w: self }
    }
    #[doc = "Bits 23:25 - MOSI signals are delayed by 80MHz clock cycles"]
    #[inline(always)]
    pub fn spi_mosi_delay_num(&mut self) -> SPI_MOSI_DELAY_NUM_W {
        SPI_MOSI_DELAY_NUM_W { w: self }
    }
    #[doc = "Bits 21:22 - MOSI signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle"]
    #[inline(always)]
    pub fn spi_mosi_delay_mode(&mut self) -> SPI_MOSI_DELAY_MODE_W {
        SPI_MOSI_DELAY_MODE_W { w: self }
    }
    #[doc = "Bits 18:20 - MISO signals are delayed by 80MHz clock cycles"]
    #[inline(always)]
    pub fn spi_miso_delay_num(&mut self) -> SPI_MISO_DELAY_NUM_W {
        SPI_MISO_DELAY_NUM_W { w: self }
    }
    #[doc = "Bits 16:17 - MISO signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle"]
    #[inline(always)]
    pub fn spi_miso_delay_mode(&mut self) -> SPI_MISO_DELAY_MODE_W {
        SPI_MISO_DELAY_MODE_W { w: self }
    }
}