1#[doc = "Register `USER1` reader"]
2pub type R = crate::R<USER1_SPEC>;
3#[doc = "Register `USER1` writer"]
4pub type W = crate::W<USER1_SPEC>;
5#[doc = "Field `USR_DUMMY_CYCLELEN` reader - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state."]
6pub type USR_DUMMY_CYCLELEN_R = crate::FieldReader;
7#[doc = "Field `USR_DUMMY_CYCLELEN` writer - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state."]
8pub type USR_DUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `MST_WFULL_ERR_END_EN` reader - 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode."]
10pub type MST_WFULL_ERR_END_EN_R = crate::BitReader;
11#[doc = "Field `MST_WFULL_ERR_END_EN` writer - 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode."]
12pub type MST_WFULL_ERR_END_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CS_SETUP_TIME` reader - (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state."]
14pub type CS_SETUP_TIME_R = crate::FieldReader;
15#[doc = "Field `CS_SETUP_TIME` writer - (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state."]
16pub type CS_SETUP_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
17#[doc = "Field `CS_HOLD_TIME` reader - delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state."]
18pub type CS_HOLD_TIME_R = crate::FieldReader;
19#[doc = "Field `CS_HOLD_TIME` writer - delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state."]
20pub type CS_HOLD_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
21#[doc = "Field `USR_ADDR_BITLEN` reader - The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state."]
22pub type USR_ADDR_BITLEN_R = crate::FieldReader;
23#[doc = "Field `USR_ADDR_BITLEN` writer - The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state."]
24pub type USR_ADDR_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
25impl R {
26 #[doc = "Bits 0:7 - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state."]
27 #[inline(always)]
28 pub fn usr_dummy_cyclelen(&self) -> USR_DUMMY_CYCLELEN_R {
29 USR_DUMMY_CYCLELEN_R::new((self.bits & 0xff) as u8)
30 }
31 #[doc = "Bit 16 - 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode."]
32 #[inline(always)]
33 pub fn mst_wfull_err_end_en(&self) -> MST_WFULL_ERR_END_EN_R {
34 MST_WFULL_ERR_END_EN_R::new(((self.bits >> 16) & 1) != 0)
35 }
36 #[doc = "Bits 17:21 - (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state."]
37 #[inline(always)]
38 pub fn cs_setup_time(&self) -> CS_SETUP_TIME_R {
39 CS_SETUP_TIME_R::new(((self.bits >> 17) & 0x1f) as u8)
40 }
41 #[doc = "Bits 22:26 - delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state."]
42 #[inline(always)]
43 pub fn cs_hold_time(&self) -> CS_HOLD_TIME_R {
44 CS_HOLD_TIME_R::new(((self.bits >> 22) & 0x1f) as u8)
45 }
46 #[doc = "Bits 27:31 - The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state."]
47 #[inline(always)]
48 pub fn usr_addr_bitlen(&self) -> USR_ADDR_BITLEN_R {
49 USR_ADDR_BITLEN_R::new(((self.bits >> 27) & 0x1f) as u8)
50 }
51}
52#[cfg(feature = "impl-register-debug")]
53impl core::fmt::Debug for R {
54 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
55 f.debug_struct("USER1")
56 .field("usr_dummy_cyclelen", &self.usr_dummy_cyclelen())
57 .field("mst_wfull_err_end_en", &self.mst_wfull_err_end_en())
58 .field("cs_setup_time", &self.cs_setup_time())
59 .field("cs_hold_time", &self.cs_hold_time())
60 .field("usr_addr_bitlen", &self.usr_addr_bitlen())
61 .finish()
62 }
63}
64impl W {
65 #[doc = "Bits 0:7 - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state."]
66 #[inline(always)]
67 pub fn usr_dummy_cyclelen(&mut self) -> USR_DUMMY_CYCLELEN_W<USER1_SPEC> {
68 USR_DUMMY_CYCLELEN_W::new(self, 0)
69 }
70 #[doc = "Bit 16 - 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode."]
71 #[inline(always)]
72 pub fn mst_wfull_err_end_en(&mut self) -> MST_WFULL_ERR_END_EN_W<USER1_SPEC> {
73 MST_WFULL_ERR_END_EN_W::new(self, 16)
74 }
75 #[doc = "Bits 17:21 - (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state."]
76 #[inline(always)]
77 pub fn cs_setup_time(&mut self) -> CS_SETUP_TIME_W<USER1_SPEC> {
78 CS_SETUP_TIME_W::new(self, 17)
79 }
80 #[doc = "Bits 22:26 - delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state."]
81 #[inline(always)]
82 pub fn cs_hold_time(&mut self) -> CS_HOLD_TIME_W<USER1_SPEC> {
83 CS_HOLD_TIME_W::new(self, 22)
84 }
85 #[doc = "Bits 27:31 - The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state."]
86 #[inline(always)]
87 pub fn usr_addr_bitlen(&mut self) -> USR_ADDR_BITLEN_W<USER1_SPEC> {
88 USR_ADDR_BITLEN_W::new(self, 27)
89 }
90}
91#[doc = "SPI USER control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`user1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`user1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
92pub struct USER1_SPEC;
93impl crate::RegisterSpec for USER1_SPEC {
94 type Ux = u32;
95}
96#[doc = "`read()` method returns [`user1::R`](R) reader structure"]
97impl crate::Readable for USER1_SPEC {}
98#[doc = "`write(|w| ..)` method takes [`user1::W`](W) writer structure"]
99impl crate::Writable for USER1_SPEC {
100 type Safety = crate::Unsafe;
101}
102#[doc = "`reset()` method sets USER1 to value 0xb841_0007"]
103impl crate::Resettable for USER1_SPEC {
104 const RESET_VALUE: u32 = 0xb841_0007;
105}