esp32s3/rtc_cntl/
state0.rs

1#[doc = "Register `STATE0` reader"]
2pub type R = crate::R<STATE0_SPEC>;
3#[doc = "Register `STATE0` writer"]
4pub type W = crate::W<STATE0_SPEC>;
5#[doc = "Field `SW_CPU_INT` writer - rtc software interrupt to main cpu"]
6pub type SW_CPU_INT_W<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `SLP_REJECT_CAUSE_CLR` writer - clear rtc sleep reject cause"]
8pub type SLP_REJECT_CAUSE_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `APB2RTC_BRIDGE_SEL` reader - 1: APB to RTC using bridge, 0: APB to RTC using sync"]
10pub type APB2RTC_BRIDGE_SEL_R = crate::BitReader;
11#[doc = "Field `APB2RTC_BRIDGE_SEL` writer - 1: APB to RTC using bridge, 0: APB to RTC using sync"]
12pub type APB2RTC_BRIDGE_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SDIO_ACTIVE_IND` reader - SDIO active indication"]
14pub type SDIO_ACTIVE_IND_R = crate::BitReader;
15#[doc = "Field `SLP_WAKEUP` reader - leep wakeup bit"]
16pub type SLP_WAKEUP_R = crate::BitReader;
17#[doc = "Field `SLP_WAKEUP` writer - leep wakeup bit"]
18pub type SLP_WAKEUP_W<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `SLP_REJECT` reader - leep reject bit"]
20pub type SLP_REJECT_R = crate::BitReader;
21#[doc = "Field `SLP_REJECT` writer - leep reject bit"]
22pub type SLP_REJECT_W<'a, REG> = crate::BitWriter<'a, REG>;
23#[doc = "Field `SLEEP_EN` reader - sleep enable bit"]
24pub type SLEEP_EN_R = crate::BitReader;
25#[doc = "Field `SLEEP_EN` writer - sleep enable bit"]
26pub type SLEEP_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
27impl R {
28    #[doc = "Bit 22 - 1: APB to RTC using bridge, 0: APB to RTC using sync"]
29    #[inline(always)]
30    pub fn apb2rtc_bridge_sel(&self) -> APB2RTC_BRIDGE_SEL_R {
31        APB2RTC_BRIDGE_SEL_R::new(((self.bits >> 22) & 1) != 0)
32    }
33    #[doc = "Bit 28 - SDIO active indication"]
34    #[inline(always)]
35    pub fn sdio_active_ind(&self) -> SDIO_ACTIVE_IND_R {
36        SDIO_ACTIVE_IND_R::new(((self.bits >> 28) & 1) != 0)
37    }
38    #[doc = "Bit 29 - leep wakeup bit"]
39    #[inline(always)]
40    pub fn slp_wakeup(&self) -> SLP_WAKEUP_R {
41        SLP_WAKEUP_R::new(((self.bits >> 29) & 1) != 0)
42    }
43    #[doc = "Bit 30 - leep reject bit"]
44    #[inline(always)]
45    pub fn slp_reject(&self) -> SLP_REJECT_R {
46        SLP_REJECT_R::new(((self.bits >> 30) & 1) != 0)
47    }
48    #[doc = "Bit 31 - sleep enable bit"]
49    #[inline(always)]
50    pub fn sleep_en(&self) -> SLEEP_EN_R {
51        SLEEP_EN_R::new(((self.bits >> 31) & 1) != 0)
52    }
53}
54#[cfg(feature = "impl-register-debug")]
55impl core::fmt::Debug for R {
56    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
57        f.debug_struct("STATE0")
58            .field("apb2rtc_bridge_sel", &self.apb2rtc_bridge_sel())
59            .field("sdio_active_ind", &self.sdio_active_ind())
60            .field("slp_wakeup", &self.slp_wakeup())
61            .field("slp_reject", &self.slp_reject())
62            .field("sleep_en", &self.sleep_en())
63            .finish()
64    }
65}
66impl W {
67    #[doc = "Bit 0 - rtc software interrupt to main cpu"]
68    #[inline(always)]
69    pub fn sw_cpu_int(&mut self) -> SW_CPU_INT_W<STATE0_SPEC> {
70        SW_CPU_INT_W::new(self, 0)
71    }
72    #[doc = "Bit 1 - clear rtc sleep reject cause"]
73    #[inline(always)]
74    pub fn slp_reject_cause_clr(&mut self) -> SLP_REJECT_CAUSE_CLR_W<STATE0_SPEC> {
75        SLP_REJECT_CAUSE_CLR_W::new(self, 1)
76    }
77    #[doc = "Bit 22 - 1: APB to RTC using bridge, 0: APB to RTC using sync"]
78    #[inline(always)]
79    pub fn apb2rtc_bridge_sel(&mut self) -> APB2RTC_BRIDGE_SEL_W<STATE0_SPEC> {
80        APB2RTC_BRIDGE_SEL_W::new(self, 22)
81    }
82    #[doc = "Bit 29 - leep wakeup bit"]
83    #[inline(always)]
84    pub fn slp_wakeup(&mut self) -> SLP_WAKEUP_W<STATE0_SPEC> {
85        SLP_WAKEUP_W::new(self, 29)
86    }
87    #[doc = "Bit 30 - leep reject bit"]
88    #[inline(always)]
89    pub fn slp_reject(&mut self) -> SLP_REJECT_W<STATE0_SPEC> {
90        SLP_REJECT_W::new(self, 30)
91    }
92    #[doc = "Bit 31 - sleep enable bit"]
93    #[inline(always)]
94    pub fn sleep_en(&mut self) -> SLEEP_EN_W<STATE0_SPEC> {
95        SLEEP_EN_W::new(self, 31)
96    }
97}
98#[doc = "configure chip sleep\n\nYou can [`read`](crate::Reg::read) this register and get [`state0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`state0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
99pub struct STATE0_SPEC;
100impl crate::RegisterSpec for STATE0_SPEC {
101    type Ux = u32;
102}
103#[doc = "`read()` method returns [`state0::R`](R) reader structure"]
104impl crate::Readable for STATE0_SPEC {}
105#[doc = "`write(|w| ..)` method takes [`state0::W`](W) writer structure"]
106impl crate::Writable for STATE0_SPEC {
107    type Safety = crate::Unsafe;
108}
109#[doc = "`reset()` method sets STATE0 to value 0"]
110impl crate::Resettable for STATE0_SPEC {}
esp32s3/rtc_cntl/state0.rs

esp32s3/rtc_cntl/
state0.rs
