1#[doc = "Register `SYS_CONF` reader"]
2pub type R = crate::R<SYS_CONF_SPEC>;
3#[doc = "Register `SYS_CONF` writer"]
4pub type W = crate::W<SYS_CONF_SPEC>;
5#[doc = "Field `APB_FIFO_MASK` reader - 1'h1: access memory directly. 1'h0: access memory by FIFO."]
6pub type APB_FIFO_MASK_R = crate::BitReader;
7#[doc = "Field `APB_FIFO_MASK` writer - 1'h1: access memory directly. 1'h0: access memory by FIFO."]
8pub type APB_FIFO_MASK_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `MEM_CLK_FORCE_ON` reader - Set this bit to enable the clock for RMT memory."]
10pub type MEM_CLK_FORCE_ON_R = crate::BitReader;
11#[doc = "Field `MEM_CLK_FORCE_ON` writer - Set this bit to enable the clock for RMT memory."]
12pub type MEM_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `MEM_FORCE_PD` reader - Set this bit to power down RMT memory."]
14pub type MEM_FORCE_PD_R = crate::BitReader;
15#[doc = "Field `MEM_FORCE_PD` writer - Set this bit to power down RMT memory."]
16pub type MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `MEM_FORCE_PU` reader - 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode."]
18pub type MEM_FORCE_PU_R = crate::BitReader;
19#[doc = "Field `MEM_FORCE_PU` writer - 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode."]
20pub type MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `SCLK_DIV_NUM` reader - the integral part of the fractional divisor"]
22pub type SCLK_DIV_NUM_R = crate::FieldReader;
23#[doc = "Field `SCLK_DIV_NUM` writer - the integral part of the fractional divisor"]
24pub type SCLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
25#[doc = "Field `SCLK_DIV_A` reader - the numerator of the fractional part of the fractional divisor"]
26pub type SCLK_DIV_A_R = crate::FieldReader;
27#[doc = "Field `SCLK_DIV_A` writer - the numerator of the fractional part of the fractional divisor"]
28pub type SCLK_DIV_A_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
29#[doc = "Field `SCLK_DIV_B` reader - the denominator of the fractional part of the fractional divisor"]
30pub type SCLK_DIV_B_R = crate::FieldReader;
31#[doc = "Field `SCLK_DIV_B` writer - the denominator of the fractional part of the fractional divisor"]
32pub type SCLK_DIV_B_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
33#[doc = "Field `SCLK_SEL` reader - choose the clock source of rmt_sclk. 1:CLK_80Mhz;2:CLK_8MHz; 2:XTAL"]
34pub type SCLK_SEL_R = crate::FieldReader;
35#[doc = "Field `SCLK_SEL` writer - choose the clock source of rmt_sclk. 1:CLK_80Mhz;2:CLK_8MHz; 2:XTAL"]
36pub type SCLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
37#[doc = "Field `SCLK_ACTIVE` reader - rmt_sclk switch"]
38pub type SCLK_ACTIVE_R = crate::BitReader;
39#[doc = "Field `SCLK_ACTIVE` writer - rmt_sclk switch"]
40pub type SCLK_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `CLK_EN` reader - RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers"]
42pub type CLK_EN_R = crate::BitReader;
43#[doc = "Field `CLK_EN` writer - RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers"]
44pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
45impl R {
46 #[doc = "Bit 0 - 1'h1: access memory directly. 1'h0: access memory by FIFO."]
47 #[inline(always)]
48 pub fn apb_fifo_mask(&self) -> APB_FIFO_MASK_R {
49 APB_FIFO_MASK_R::new((self.bits & 1) != 0)
50 }
51 #[doc = "Bit 1 - Set this bit to enable the clock for RMT memory."]
52 #[inline(always)]
53 pub fn mem_clk_force_on(&self) -> MEM_CLK_FORCE_ON_R {
54 MEM_CLK_FORCE_ON_R::new(((self.bits >> 1) & 1) != 0)
55 }
56 #[doc = "Bit 2 - Set this bit to power down RMT memory."]
57 #[inline(always)]
58 pub fn mem_force_pd(&self) -> MEM_FORCE_PD_R {
59 MEM_FORCE_PD_R::new(((self.bits >> 2) & 1) != 0)
60 }
61 #[doc = "Bit 3 - 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode."]
62 #[inline(always)]
63 pub fn mem_force_pu(&self) -> MEM_FORCE_PU_R {
64 MEM_FORCE_PU_R::new(((self.bits >> 3) & 1) != 0)
65 }
66 #[doc = "Bits 4:11 - the integral part of the fractional divisor"]
67 #[inline(always)]
68 pub fn sclk_div_num(&self) -> SCLK_DIV_NUM_R {
69 SCLK_DIV_NUM_R::new(((self.bits >> 4) & 0xff) as u8)
70 }
71 #[doc = "Bits 12:17 - the numerator of the fractional part of the fractional divisor"]
72 #[inline(always)]
73 pub fn sclk_div_a(&self) -> SCLK_DIV_A_R {
74 SCLK_DIV_A_R::new(((self.bits >> 12) & 0x3f) as u8)
75 }
76 #[doc = "Bits 18:23 - the denominator of the fractional part of the fractional divisor"]
77 #[inline(always)]
78 pub fn sclk_div_b(&self) -> SCLK_DIV_B_R {
79 SCLK_DIV_B_R::new(((self.bits >> 18) & 0x3f) as u8)
80 }
81 #[doc = "Bits 24:25 - choose the clock source of rmt_sclk. 1:CLK_80Mhz;2:CLK_8MHz; 2:XTAL"]
82 #[inline(always)]
83 pub fn sclk_sel(&self) -> SCLK_SEL_R {
84 SCLK_SEL_R::new(((self.bits >> 24) & 3) as u8)
85 }
86 #[doc = "Bit 26 - rmt_sclk switch"]
87 #[inline(always)]
88 pub fn sclk_active(&self) -> SCLK_ACTIVE_R {
89 SCLK_ACTIVE_R::new(((self.bits >> 26) & 1) != 0)
90 }
91 #[doc = "Bit 31 - RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers"]
92 #[inline(always)]
93 pub fn clk_en(&self) -> CLK_EN_R {
94 CLK_EN_R::new(((self.bits >> 31) & 1) != 0)
95 }
96}
97#[cfg(feature = "impl-register-debug")]
98impl core::fmt::Debug for R {
99 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
100 f.debug_struct("SYS_CONF")
101 .field("apb_fifo_mask", &self.apb_fifo_mask())
102 .field("mem_clk_force_on", &self.mem_clk_force_on())
103 .field("mem_force_pd", &self.mem_force_pd())
104 .field("mem_force_pu", &self.mem_force_pu())
105 .field("sclk_div_num", &self.sclk_div_num())
106 .field("sclk_div_a", &self.sclk_div_a())
107 .field("sclk_div_b", &self.sclk_div_b())
108 .field("sclk_sel", &self.sclk_sel())
109 .field("sclk_active", &self.sclk_active())
110 .field("clk_en", &self.clk_en())
111 .finish()
112 }
113}
114impl W {
115 #[doc = "Bit 0 - 1'h1: access memory directly. 1'h0: access memory by FIFO."]
116 #[inline(always)]
117 pub fn apb_fifo_mask(&mut self) -> APB_FIFO_MASK_W<SYS_CONF_SPEC> {
118 APB_FIFO_MASK_W::new(self, 0)
119 }
120 #[doc = "Bit 1 - Set this bit to enable the clock for RMT memory."]
121 #[inline(always)]
122 pub fn mem_clk_force_on(&mut self) -> MEM_CLK_FORCE_ON_W<SYS_CONF_SPEC> {
123 MEM_CLK_FORCE_ON_W::new(self, 1)
124 }
125 #[doc = "Bit 2 - Set this bit to power down RMT memory."]
126 #[inline(always)]
127 pub fn mem_force_pd(&mut self) -> MEM_FORCE_PD_W<SYS_CONF_SPEC> {
128 MEM_FORCE_PD_W::new(self, 2)
129 }
130 #[doc = "Bit 3 - 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode."]
131 #[inline(always)]
132 pub fn mem_force_pu(&mut self) -> MEM_FORCE_PU_W<SYS_CONF_SPEC> {
133 MEM_FORCE_PU_W::new(self, 3)
134 }
135 #[doc = "Bits 4:11 - the integral part of the fractional divisor"]
136 #[inline(always)]
137 pub fn sclk_div_num(&mut self) -> SCLK_DIV_NUM_W<SYS_CONF_SPEC> {
138 SCLK_DIV_NUM_W::new(self, 4)
139 }
140 #[doc = "Bits 12:17 - the numerator of the fractional part of the fractional divisor"]
141 #[inline(always)]
142 pub fn sclk_div_a(&mut self) -> SCLK_DIV_A_W<SYS_CONF_SPEC> {
143 SCLK_DIV_A_W::new(self, 12)
144 }
145 #[doc = "Bits 18:23 - the denominator of the fractional part of the fractional divisor"]
146 #[inline(always)]
147 pub fn sclk_div_b(&mut self) -> SCLK_DIV_B_W<SYS_CONF_SPEC> {
148 SCLK_DIV_B_W::new(self, 18)
149 }
150 #[doc = "Bits 24:25 - choose the clock source of rmt_sclk. 1:CLK_80Mhz;2:CLK_8MHz; 2:XTAL"]
151 #[inline(always)]
152 pub fn sclk_sel(&mut self) -> SCLK_SEL_W<SYS_CONF_SPEC> {
153 SCLK_SEL_W::new(self, 24)
154 }
155 #[doc = "Bit 26 - rmt_sclk switch"]
156 #[inline(always)]
157 pub fn sclk_active(&mut self) -> SCLK_ACTIVE_W<SYS_CONF_SPEC> {
158 SCLK_ACTIVE_W::new(self, 26)
159 }
160 #[doc = "Bit 31 - RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers"]
161 #[inline(always)]
162 pub fn clk_en(&mut self) -> CLK_EN_W<SYS_CONF_SPEC> {
163 CLK_EN_W::new(self, 31)
164 }
165}
166#[doc = "RMT apb configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`sys_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sys_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
167pub struct SYS_CONF_SPEC;
168impl crate::RegisterSpec for SYS_CONF_SPEC {
169 type Ux = u32;
170}
171#[doc = "`read()` method returns [`sys_conf::R`](R) reader structure"]
172impl crate::Readable for SYS_CONF_SPEC {}
173#[doc = "`write(|w| ..)` method takes [`sys_conf::W`](W) writer structure"]
174impl crate::Writable for SYS_CONF_SPEC {
175 type Safety = crate::Unsafe;
176}
177#[doc = "`reset()` method sets SYS_CONF to value 0x0500_0010"]
178impl crate::Resettable for SYS_CONF_SPEC {
179 const RESET_VALUE: u32 = 0x0500_0010;
180}