esp32s3/lcd_cam/
lcd_data_dout_mode.rs1#[doc = "Register `LCD_DATA_DOUT_MODE` reader"]
2pub type R = crate::R<LCD_DATA_DOUT_MODE_SPEC>;
3#[doc = "Register `LCD_DATA_DOUT_MODE` writer"]
4pub type W = crate::W<LCD_DATA_DOUT_MODE_SPEC>;
5#[doc = "The output data bit %s is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK.\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum DELAY_MODE {
10 #[doc = "0: Output without delay"]
11 None = 0,
12 #[doc = "1: Delayed by the rising edge of LCD_CLK"]
13 RaisingEdge = 1,
14 #[doc = "2: Delayed by the falling edge of LCD_CLK"]
15 FallingEdge = 2,
16}
17impl From<DELAY_MODE> for u8 {
18 #[inline(always)]
19 fn from(variant: DELAY_MODE) -> Self {
20 variant as _
21 }
22}
23impl crate::FieldSpec for DELAY_MODE {
24 type Ux = u8;
25}
26impl crate::IsEnum for DELAY_MODE {}
27#[doc = "Field `DOUT_MODE(0-15)` reader - The output data bit %s is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
28pub type DOUT_MODE_R = crate::FieldReader<DELAY_MODE>;
29impl DOUT_MODE_R {
30 #[doc = "Get enumerated values variant"]
31 #[inline(always)]
32 pub const fn variant(&self) -> Option<DELAY_MODE> {
33 match self.bits {
34 0 => Some(DELAY_MODE::None),
35 1 => Some(DELAY_MODE::RaisingEdge),
36 2 => Some(DELAY_MODE::FallingEdge),
37 _ => None,
38 }
39 }
40 #[doc = "Output without delay"]
41 #[inline(always)]
42 pub fn is_none(&self) -> bool {
43 *self == DELAY_MODE::None
44 }
45 #[doc = "Delayed by the rising edge of LCD_CLK"]
46 #[inline(always)]
47 pub fn is_raising_edge(&self) -> bool {
48 *self == DELAY_MODE::RaisingEdge
49 }
50 #[doc = "Delayed by the falling edge of LCD_CLK"]
51 #[inline(always)]
52 pub fn is_falling_edge(&self) -> bool {
53 *self == DELAY_MODE::FallingEdge
54 }
55}
56#[doc = "Field `DOUT_MODE(0-15)` writer - The output data bit %s is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
57pub type DOUT_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DELAY_MODE>;
58impl<'a, REG> DOUT_MODE_W<'a, REG>
59where
60 REG: crate::Writable + crate::RegisterSpec,
61 REG::Ux: From<u8>,
62{
63 #[doc = "Output without delay"]
64 #[inline(always)]
65 pub fn none(self) -> &'a mut crate::W<REG> {
66 self.variant(DELAY_MODE::None)
67 }
68 #[doc = "Delayed by the rising edge of LCD_CLK"]
69 #[inline(always)]
70 pub fn raising_edge(self) -> &'a mut crate::W<REG> {
71 self.variant(DELAY_MODE::RaisingEdge)
72 }
73 #[doc = "Delayed by the falling edge of LCD_CLK"]
74 #[inline(always)]
75 pub fn falling_edge(self) -> &'a mut crate::W<REG> {
76 self.variant(DELAY_MODE::FallingEdge)
77 }
78}
79impl R {
80 #[doc = "The output data bit (0-15) is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
81 #[doc = ""]
82 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DOUT0_MODE` field.</div>"]
83 #[inline(always)]
84 pub fn dout_mode(&self, n: u8) -> DOUT_MODE_R {
85 #[allow(clippy::no_effect)]
86 [(); 16][n as usize];
87 DOUT_MODE_R::new(((self.bits >> (n * 2)) & 3) as u8)
88 }
89 #[doc = "Iterator for array of:"]
90 #[doc = "The output data bit (0-15) is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
91 #[inline(always)]
92 pub fn dout_mode_iter(&self) -> impl Iterator<Item = DOUT_MODE_R> + '_ {
93 (0..16).map(move |n| DOUT_MODE_R::new(((self.bits >> (n * 2)) & 3) as u8))
94 }
95 #[doc = "Bits 0:1 - The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
96 #[inline(always)]
97 pub fn dout0_mode(&self) -> DOUT_MODE_R {
98 DOUT_MODE_R::new((self.bits & 3) as u8)
99 }
100 #[doc = "Bits 2:3 - The output data bit 1 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
101 #[inline(always)]
102 pub fn dout1_mode(&self) -> DOUT_MODE_R {
103 DOUT_MODE_R::new(((self.bits >> 2) & 3) as u8)
104 }
105 #[doc = "Bits 4:5 - The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
106 #[inline(always)]
107 pub fn dout2_mode(&self) -> DOUT_MODE_R {
108 DOUT_MODE_R::new(((self.bits >> 4) & 3) as u8)
109 }
110 #[doc = "Bits 6:7 - The output data bit 3 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
111 #[inline(always)]
112 pub fn dout3_mode(&self) -> DOUT_MODE_R {
113 DOUT_MODE_R::new(((self.bits >> 6) & 3) as u8)
114 }
115 #[doc = "Bits 8:9 - The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
116 #[inline(always)]
117 pub fn dout4_mode(&self) -> DOUT_MODE_R {
118 DOUT_MODE_R::new(((self.bits >> 8) & 3) as u8)
119 }
120 #[doc = "Bits 10:11 - The output data bit 5 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
121 #[inline(always)]
122 pub fn dout5_mode(&self) -> DOUT_MODE_R {
123 DOUT_MODE_R::new(((self.bits >> 10) & 3) as u8)
124 }
125 #[doc = "Bits 12:13 - The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
126 #[inline(always)]
127 pub fn dout6_mode(&self) -> DOUT_MODE_R {
128 DOUT_MODE_R::new(((self.bits >> 12) & 3) as u8)
129 }
130 #[doc = "Bits 14:15 - The output data bit 7 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
131 #[inline(always)]
132 pub fn dout7_mode(&self) -> DOUT_MODE_R {
133 DOUT_MODE_R::new(((self.bits >> 14) & 3) as u8)
134 }
135 #[doc = "Bits 16:17 - The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
136 #[inline(always)]
137 pub fn dout8_mode(&self) -> DOUT_MODE_R {
138 DOUT_MODE_R::new(((self.bits >> 16) & 3) as u8)
139 }
140 #[doc = "Bits 18:19 - The output data bit 9 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
141 #[inline(always)]
142 pub fn dout9_mode(&self) -> DOUT_MODE_R {
143 DOUT_MODE_R::new(((self.bits >> 18) & 3) as u8)
144 }
145 #[doc = "Bits 20:21 - The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
146 #[inline(always)]
147 pub fn dout10_mode(&self) -> DOUT_MODE_R {
148 DOUT_MODE_R::new(((self.bits >> 20) & 3) as u8)
149 }
150 #[doc = "Bits 22:23 - The output data bit 11 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
151 #[inline(always)]
152 pub fn dout11_mode(&self) -> DOUT_MODE_R {
153 DOUT_MODE_R::new(((self.bits >> 22) & 3) as u8)
154 }
155 #[doc = "Bits 24:25 - The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
156 #[inline(always)]
157 pub fn dout12_mode(&self) -> DOUT_MODE_R {
158 DOUT_MODE_R::new(((self.bits >> 24) & 3) as u8)
159 }
160 #[doc = "Bits 26:27 - The output data bit 13 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
161 #[inline(always)]
162 pub fn dout13_mode(&self) -> DOUT_MODE_R {
163 DOUT_MODE_R::new(((self.bits >> 26) & 3) as u8)
164 }
165 #[doc = "Bits 28:29 - The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
166 #[inline(always)]
167 pub fn dout14_mode(&self) -> DOUT_MODE_R {
168 DOUT_MODE_R::new(((self.bits >> 28) & 3) as u8)
169 }
170 #[doc = "Bits 30:31 - The output data bit 15 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
171 #[inline(always)]
172 pub fn dout15_mode(&self) -> DOUT_MODE_R {
173 DOUT_MODE_R::new(((self.bits >> 30) & 3) as u8)
174 }
175}
176#[cfg(feature = "impl-register-debug")]
177impl core::fmt::Debug for R {
178 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
179 f.debug_struct("LCD_DATA_DOUT_MODE")
180 .field("dout0_mode", &self.dout0_mode())
181 .field("dout1_mode", &self.dout1_mode())
182 .field("dout2_mode", &self.dout2_mode())
183 .field("dout3_mode", &self.dout3_mode())
184 .field("dout4_mode", &self.dout4_mode())
185 .field("dout5_mode", &self.dout5_mode())
186 .field("dout6_mode", &self.dout6_mode())
187 .field("dout7_mode", &self.dout7_mode())
188 .field("dout8_mode", &self.dout8_mode())
189 .field("dout9_mode", &self.dout9_mode())
190 .field("dout10_mode", &self.dout10_mode())
191 .field("dout11_mode", &self.dout11_mode())
192 .field("dout12_mode", &self.dout12_mode())
193 .field("dout13_mode", &self.dout13_mode())
194 .field("dout14_mode", &self.dout14_mode())
195 .field("dout15_mode", &self.dout15_mode())
196 .finish()
197 }
198}
199impl W {
200 #[doc = "The output data bit (0-15) is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
201 #[doc = ""]
202 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DOUT0_MODE` field.</div>"]
203 #[inline(always)]
204 pub fn dout_mode(&mut self, n: u8) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
205 #[allow(clippy::no_effect)]
206 [(); 16][n as usize];
207 DOUT_MODE_W::new(self, n * 2)
208 }
209 #[doc = "Bits 0:1 - The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
210 #[inline(always)]
211 pub fn dout0_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
212 DOUT_MODE_W::new(self, 0)
213 }
214 #[doc = "Bits 2:3 - The output data bit 1 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
215 #[inline(always)]
216 pub fn dout1_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
217 DOUT_MODE_W::new(self, 2)
218 }
219 #[doc = "Bits 4:5 - The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
220 #[inline(always)]
221 pub fn dout2_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
222 DOUT_MODE_W::new(self, 4)
223 }
224 #[doc = "Bits 6:7 - The output data bit 3 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
225 #[inline(always)]
226 pub fn dout3_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
227 DOUT_MODE_W::new(self, 6)
228 }
229 #[doc = "Bits 8:9 - The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
230 #[inline(always)]
231 pub fn dout4_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
232 DOUT_MODE_W::new(self, 8)
233 }
234 #[doc = "Bits 10:11 - The output data bit 5 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
235 #[inline(always)]
236 pub fn dout5_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
237 DOUT_MODE_W::new(self, 10)
238 }
239 #[doc = "Bits 12:13 - The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
240 #[inline(always)]
241 pub fn dout6_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
242 DOUT_MODE_W::new(self, 12)
243 }
244 #[doc = "Bits 14:15 - The output data bit 7 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
245 #[inline(always)]
246 pub fn dout7_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
247 DOUT_MODE_W::new(self, 14)
248 }
249 #[doc = "Bits 16:17 - The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
250 #[inline(always)]
251 pub fn dout8_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
252 DOUT_MODE_W::new(self, 16)
253 }
254 #[doc = "Bits 18:19 - The output data bit 9 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
255 #[inline(always)]
256 pub fn dout9_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
257 DOUT_MODE_W::new(self, 18)
258 }
259 #[doc = "Bits 20:21 - The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
260 #[inline(always)]
261 pub fn dout10_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
262 DOUT_MODE_W::new(self, 20)
263 }
264 #[doc = "Bits 22:23 - The output data bit 11 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
265 #[inline(always)]
266 pub fn dout11_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
267 DOUT_MODE_W::new(self, 22)
268 }
269 #[doc = "Bits 24:25 - The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
270 #[inline(always)]
271 pub fn dout12_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
272 DOUT_MODE_W::new(self, 24)
273 }
274 #[doc = "Bits 26:27 - The output data bit 13 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
275 #[inline(always)]
276 pub fn dout13_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
277 DOUT_MODE_W::new(self, 26)
278 }
279 #[doc = "Bits 28:29 - The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
280 #[inline(always)]
281 pub fn dout14_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
282 DOUT_MODE_W::new(self, 28)
283 }
284 #[doc = "Bits 30:31 - The output data bit 15 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
285 #[inline(always)]
286 pub fn dout15_mode(&mut self) -> DOUT_MODE_W<LCD_DATA_DOUT_MODE_SPEC> {
287 DOUT_MODE_W::new(self, 30)
288 }
289}
290#[doc = "LCD data delay configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_data_dout_mode::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_data_dout_mode::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
291pub struct LCD_DATA_DOUT_MODE_SPEC;
292impl crate::RegisterSpec for LCD_DATA_DOUT_MODE_SPEC {
293 type Ux = u32;
294}
295#[doc = "`read()` method returns [`lcd_data_dout_mode::R`](R) reader structure"]
296impl crate::Readable for LCD_DATA_DOUT_MODE_SPEC {}
297#[doc = "`write(|w| ..)` method takes [`lcd_data_dout_mode::W`](W) writer structure"]
298impl crate::Writable for LCD_DATA_DOUT_MODE_SPEC {
299 type Safety = crate::Unsafe;
300}
301#[doc = "`reset()` method sets LCD_DATA_DOUT_MODE to value 0"]
302impl crate::Resettable for LCD_DATA_DOUT_MODE_SPEC {}