esp32s3/extmem/
icache_ctrl1.rs

1#[doc = "Register `ICACHE_CTRL1` reader"]
2pub type R = crate::R<ICACHE_CTRL1_SPEC>;
3#[doc = "Register `ICACHE_CTRL1` writer"]
4pub type W = crate::W<ICACHE_CTRL1_SPEC>;
5#[doc = "Field `ICACHE_SHUT_CORE0_BUS` reader - The bit is used to disable core0 ibus, 0: enable, 1: disable"]
6pub type ICACHE_SHUT_CORE0_BUS_R = crate::BitReader;
7#[doc = "Field `ICACHE_SHUT_CORE0_BUS` writer - The bit is used to disable core0 ibus, 0: enable, 1: disable"]
8pub type ICACHE_SHUT_CORE0_BUS_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ICACHE_SHUT_CORE1_BUS` reader - The bit is used to disable core1 ibus, 0: enable, 1: disable"]
10pub type ICACHE_SHUT_CORE1_BUS_R = crate::BitReader;
11#[doc = "Field `ICACHE_SHUT_CORE1_BUS` writer - The bit is used to disable core1 ibus, 0: enable, 1: disable"]
12pub type ICACHE_SHUT_CORE1_BUS_W<'a, REG> = crate::BitWriter<'a, REG>;
13impl R {
14    #[doc = "Bit 0 - The bit is used to disable core0 ibus, 0: enable, 1: disable"]
15    #[inline(always)]
16    pub fn icache_shut_core0_bus(&self) -> ICACHE_SHUT_CORE0_BUS_R {
17        ICACHE_SHUT_CORE0_BUS_R::new((self.bits & 1) != 0)
18    }
19    #[doc = "Bit 1 - The bit is used to disable core1 ibus, 0: enable, 1: disable"]
20    #[inline(always)]
21    pub fn icache_shut_core1_bus(&self) -> ICACHE_SHUT_CORE1_BUS_R {
22        ICACHE_SHUT_CORE1_BUS_R::new(((self.bits >> 1) & 1) != 0)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("ICACHE_CTRL1")
29            .field("icache_shut_core0_bus", &self.icache_shut_core0_bus())
30            .field("icache_shut_core1_bus", &self.icache_shut_core1_bus())
31            .finish()
32    }
33}
34impl W {
35    #[doc = "Bit 0 - The bit is used to disable core0 ibus, 0: enable, 1: disable"]
36    #[inline(always)]
37    pub fn icache_shut_core0_bus(&mut self) -> ICACHE_SHUT_CORE0_BUS_W<ICACHE_CTRL1_SPEC> {
38        ICACHE_SHUT_CORE0_BUS_W::new(self, 0)
39    }
40    #[doc = "Bit 1 - The bit is used to disable core1 ibus, 0: enable, 1: disable"]
41    #[inline(always)]
42    pub fn icache_shut_core1_bus(&mut self) -> ICACHE_SHUT_CORE1_BUS_W<ICACHE_CTRL1_SPEC> {
43        ICACHE_SHUT_CORE1_BUS_W::new(self, 1)
44    }
45}
46#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
47pub struct ICACHE_CTRL1_SPEC;
48impl crate::RegisterSpec for ICACHE_CTRL1_SPEC {
49    type Ux = u32;
50}
51#[doc = "`read()` method returns [`icache_ctrl1::R`](R) reader structure"]
52impl crate::Readable for ICACHE_CTRL1_SPEC {}
53#[doc = "`write(|w| ..)` method takes [`icache_ctrl1::W`](W) writer structure"]
54impl crate::Writable for ICACHE_CTRL1_SPEC {
55    type Safety = crate::Unsafe;
56}
57#[doc = "`reset()` method sets ICACHE_CTRL1 to value 0x03"]
58impl crate::Resettable for ICACHE_CTRL1_SPEC {
59    const RESET_VALUE: u32 = 0x03;
60}
esp32s3/extmem/icache_ctrl1.rs

esp32s3/extmem/
icache_ctrl1.rs
