esp32s3/dma/ch/out_int/
clr.rs

1#[doc = "Register `CLR` writer"]
2pub type W = crate::W<CLR_SPEC>;
3#[doc = "Field `OUT_DONE` writer - Set this bit to clear the OUT_DONE_CH_INT interrupt."]
4pub type OUT_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `OUT_EOF` writer - Set this bit to clear the OUT_EOF_CH_INT interrupt."]
6pub type OUT_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `OUT_DSCR_ERR` writer - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."]
8pub type OUT_DSCR_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `OUT_TOTAL_EOF` writer - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."]
10pub type OUT_TOTAL_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[doc = "Field `OUTFIFO_OVF_L1` writer - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."]
12pub type OUTFIFO_OVF_L1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `OUTFIFO_UDF_L1` writer - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."]
14pub type OUTFIFO_UDF_L1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
15#[doc = "Field `OUTFIFO_OVF_L3` writer - Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt."]
16pub type OUTFIFO_OVF_L3_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[doc = "Field `OUTFIFO_UDF_L3` writer - Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt."]
18pub type OUTFIFO_UDF_L3_W<'a, REG> = crate::BitWriter1C<'a, REG>;
19#[cfg(feature = "impl-register-debug")]
20impl core::fmt::Debug for crate::generic::Reg<CLR_SPEC> {
21    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
22        write!(f, "(not readable)")
23    }
24}
25impl W {
26    #[doc = "Bit 0 - Set this bit to clear the OUT_DONE_CH_INT interrupt."]
27    #[inline(always)]
28    pub fn out_done(&mut self) -> OUT_DONE_W<CLR_SPEC> {
29        OUT_DONE_W::new(self, 0)
30    }
31    #[doc = "Bit 1 - Set this bit to clear the OUT_EOF_CH_INT interrupt."]
32    #[inline(always)]
33    pub fn out_eof(&mut self) -> OUT_EOF_W<CLR_SPEC> {
34        OUT_EOF_W::new(self, 1)
35    }
36    #[doc = "Bit 2 - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."]
37    #[inline(always)]
38    pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<CLR_SPEC> {
39        OUT_DSCR_ERR_W::new(self, 2)
40    }
41    #[doc = "Bit 3 - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."]
42    #[inline(always)]
43    pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<CLR_SPEC> {
44        OUT_TOTAL_EOF_W::new(self, 3)
45    }
46    #[doc = "Bit 4 - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."]
47    #[inline(always)]
48    pub fn outfifo_ovf_l1(&mut self) -> OUTFIFO_OVF_L1_W<CLR_SPEC> {
49        OUTFIFO_OVF_L1_W::new(self, 4)
50    }
51    #[doc = "Bit 5 - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."]
52    #[inline(always)]
53    pub fn outfifo_udf_l1(&mut self) -> OUTFIFO_UDF_L1_W<CLR_SPEC> {
54        OUTFIFO_UDF_L1_W::new(self, 5)
55    }
56    #[doc = "Bit 6 - Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt."]
57    #[inline(always)]
58    pub fn outfifo_ovf_l3(&mut self) -> OUTFIFO_OVF_L3_W<CLR_SPEC> {
59        OUTFIFO_OVF_L3_W::new(self, 6)
60    }
61    #[doc = "Bit 7 - Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt."]
62    #[inline(always)]
63    pub fn outfifo_udf_l3(&mut self) -> OUTFIFO_UDF_L3_W<CLR_SPEC> {
64        OUTFIFO_UDF_L3_W::new(self, 7)
65    }
66}
67#[doc = "Interrupt clear bits of Tx channel 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
68pub struct CLR_SPEC;
69impl crate::RegisterSpec for CLR_SPEC {
70    type Ux = u32;
71}
72#[doc = "`write(|w| ..)` method takes [`clr::W`](W) writer structure"]
73impl crate::Writable for CLR_SPEC {
74    type Safety = crate::Unsafe;
75    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xff;
76}
77#[doc = "`reset()` method sets CLR to value 0"]
78impl crate::Resettable for CLR_SPEC {}
esp32s3/dma/ch/out_int/clr.rs

esp32s3/dma/ch/out_int/
clr.rs
