esp32s3/dma/ch/in_int/
clr.rs

1#[doc = "Register `CLR` writer"]
2pub type W = crate::W<CLR_SPEC>;
3#[doc = "Field `IN_DONE` writer - Set this bit to clear the IN_DONE_CH_INT interrupt."]
4pub type IN_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `IN_SUC_EOF` writer - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."]
6pub type IN_SUC_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `IN_ERR_EOF` writer - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."]
8pub type IN_ERR_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `IN_DSCR_ERR` writer - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt."]
10pub type IN_DSCR_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[doc = "Field `IN_DSCR_EMPTY` writer - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."]
12pub type IN_DSCR_EMPTY_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `DMA_INFIFO_FULL_WM` writer - Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt."]
14pub type DMA_INFIFO_FULL_WM_W<'a, REG> = crate::BitWriter1C<'a, REG>;
15#[doc = "Field `INFIFO_OVF_L1` writer - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."]
16pub type INFIFO_OVF_L1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[doc = "Field `INFIFO_UDF_L1` writer - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."]
18pub type INFIFO_UDF_L1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
19#[doc = "Field `INFIFO_OVF_L3` writer - Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt."]
20pub type INFIFO_OVF_L3_W<'a, REG> = crate::BitWriter1C<'a, REG>;
21#[doc = "Field `INFIFO_UDF_L3` writer - Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt."]
22pub type INFIFO_UDF_L3_W<'a, REG> = crate::BitWriter1C<'a, REG>;
23#[cfg(feature = "impl-register-debug")]
24impl core::fmt::Debug for crate::generic::Reg<CLR_SPEC> {
25    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
26        write!(f, "(not readable)")
27    }
28}
29impl W {
30    #[doc = "Bit 0 - Set this bit to clear the IN_DONE_CH_INT interrupt."]
31    #[inline(always)]
32    pub fn in_done(&mut self) -> IN_DONE_W<CLR_SPEC> {
33        IN_DONE_W::new(self, 0)
34    }
35    #[doc = "Bit 1 - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."]
36    #[inline(always)]
37    pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<CLR_SPEC> {
38        IN_SUC_EOF_W::new(self, 1)
39    }
40    #[doc = "Bit 2 - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."]
41    #[inline(always)]
42    pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<CLR_SPEC> {
43        IN_ERR_EOF_W::new(self, 2)
44    }
45    #[doc = "Bit 3 - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt."]
46    #[inline(always)]
47    pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<CLR_SPEC> {
48        IN_DSCR_ERR_W::new(self, 3)
49    }
50    #[doc = "Bit 4 - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."]
51    #[inline(always)]
52    pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<CLR_SPEC> {
53        IN_DSCR_EMPTY_W::new(self, 4)
54    }
55    #[doc = "Bit 5 - Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt."]
56    #[inline(always)]
57    pub fn dma_infifo_full_wm(&mut self) -> DMA_INFIFO_FULL_WM_W<CLR_SPEC> {
58        DMA_INFIFO_FULL_WM_W::new(self, 5)
59    }
60    #[doc = "Bit 6 - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."]
61    #[inline(always)]
62    pub fn infifo_ovf_l1(&mut self) -> INFIFO_OVF_L1_W<CLR_SPEC> {
63        INFIFO_OVF_L1_W::new(self, 6)
64    }
65    #[doc = "Bit 7 - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."]
66    #[inline(always)]
67    pub fn infifo_udf_l1(&mut self) -> INFIFO_UDF_L1_W<CLR_SPEC> {
68        INFIFO_UDF_L1_W::new(self, 7)
69    }
70    #[doc = "Bit 8 - Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt."]
71    #[inline(always)]
72    pub fn infifo_ovf_l3(&mut self) -> INFIFO_OVF_L3_W<CLR_SPEC> {
73        INFIFO_OVF_L3_W::new(self, 8)
74    }
75    #[doc = "Bit 9 - Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt."]
76    #[inline(always)]
77    pub fn infifo_udf_l3(&mut self) -> INFIFO_UDF_L3_W<CLR_SPEC> {
78        INFIFO_UDF_L3_W::new(self, 9)
79    }
80}
81#[doc = "Interrupt clear bits of Rx channel 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
82pub struct CLR_SPEC;
83impl crate::RegisterSpec for CLR_SPEC {
84    type Ux = u32;
85}
86#[doc = "`write(|w| ..)` method takes [`clr::W`](W) writer structure"]
87impl crate::Writable for CLR_SPEC {
88    type Safety = crate::Unsafe;
89    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x03ff;
90}
91#[doc = "`reset()` method sets CLR to value 0"]
92impl crate::Resettable for CLR_SPEC {}
esp32s3/dma/ch/in_int/clr.rs

esp32s3/dma/ch/in_int/
clr.rs
