1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CTRL_SPEC>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CTRL_SPEC>;
5#[doc = "Field `START_FORCE` reader - enable start saradc by sw"]
6pub type START_FORCE_R = crate::BitReader;
7#[doc = "Field `START_FORCE` writer - enable start saradc by sw"]
8pub type START_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `START` reader - start saradc by sw"]
10pub type START_R = crate::BitReader;
11#[doc = "Field `START` writer - start saradc by sw"]
12pub type START_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `WORK_MODE` reader - 0: single mode, 1: double mode, 2: alternate mode"]
14pub type WORK_MODE_R = crate::FieldReader;
15#[doc = "Field `WORK_MODE` writer - 0: single mode, 1: double mode, 2: alternate mode"]
16pub type WORK_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17#[doc = "Field `SAR_SEL` reader - 0: SAR1, 1: SAR2, only work for single SAR mode"]
18pub type SAR_SEL_R = crate::BitReader;
19#[doc = "Field `SAR_SEL` writer - 0: SAR1, 1: SAR2, only work for single SAR mode"]
20pub type SAR_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `SAR_CLK_GATED` reader - enable SAR CLK gate when saradc idle"]
22pub type SAR_CLK_GATED_R = crate::BitReader;
23#[doc = "Field `SAR_CLK_GATED` writer - enable SAR CLK gate when saradc idle"]
24pub type SAR_CLK_GATED_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `SAR_CLK_DIV` reader - SAR clock divider"]
26pub type SAR_CLK_DIV_R = crate::FieldReader;
27#[doc = "Field `SAR_CLK_DIV` writer - SAR clock divider"]
28pub type SAR_CLK_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
29#[doc = "Field `SAR1_PATT_LEN` reader - 0 ~ 15 means length 1 ~ 16"]
30pub type SAR1_PATT_LEN_R = crate::FieldReader;
31#[doc = "Field `SAR1_PATT_LEN` writer - 0 ~ 15 means length 1 ~ 16"]
32pub type SAR1_PATT_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
33#[doc = "Field `SAR2_PATT_LEN` reader - 0 ~ 15 means length 1 ~ 16"]
34pub type SAR2_PATT_LEN_R = crate::FieldReader;
35#[doc = "Field `SAR2_PATT_LEN` writer - 0 ~ 15 means length 1 ~ 16"]
36pub type SAR2_PATT_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
37#[doc = "Field `SAR1_PATT_P_CLEAR` reader - clear the pointer of pattern table for DIG ADC1 CTRL"]
38pub type SAR1_PATT_P_CLEAR_R = crate::BitReader;
39#[doc = "Field `SAR1_PATT_P_CLEAR` writer - clear the pointer of pattern table for DIG ADC1 CTRL"]
40pub type SAR1_PATT_P_CLEAR_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `SAR2_PATT_P_CLEAR` reader - clear the pointer of pattern table for DIG ADC2 CTRL"]
42pub type SAR2_PATT_P_CLEAR_R = crate::BitReader;
43#[doc = "Field `SAR2_PATT_P_CLEAR` writer - clear the pointer of pattern table for DIG ADC2 CTRL"]
44pub type SAR2_PATT_P_CLEAR_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `DATA_SAR_SEL` reader - 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits."]
46pub type DATA_SAR_SEL_R = crate::BitReader;
47#[doc = "Field `DATA_SAR_SEL` writer - 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits."]
48pub type DATA_SAR_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `DATA_TO_I2S` reader - 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix"]
50pub type DATA_TO_I2S_R = crate::BitReader;
51#[doc = "Field `DATA_TO_I2S` writer - 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix"]
52pub type DATA_TO_I2S_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `XPD_SAR_FORCE` reader - force option to xpd sar blocks"]
54pub type XPD_SAR_FORCE_R = crate::FieldReader;
55#[doc = "Field `XPD_SAR_FORCE` writer - force option to xpd sar blocks"]
56pub type XPD_SAR_FORCE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
57#[doc = "Field `WAIT_ARB_CYCLE` reader - wait arbit signal stable after sar_done"]
58pub type WAIT_ARB_CYCLE_R = crate::FieldReader;
59#[doc = "Field `WAIT_ARB_CYCLE` writer - wait arbit signal stable after sar_done"]
60pub type WAIT_ARB_CYCLE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
61impl R {
62 #[doc = "Bit 0 - enable start saradc by sw"]
63 #[inline(always)]
64 pub fn start_force(&self) -> START_FORCE_R {
65 START_FORCE_R::new((self.bits & 1) != 0)
66 }
67 #[doc = "Bit 1 - start saradc by sw"]
68 #[inline(always)]
69 pub fn start(&self) -> START_R {
70 START_R::new(((self.bits >> 1) & 1) != 0)
71 }
72 #[doc = "Bits 3:4 - 0: single mode, 1: double mode, 2: alternate mode"]
73 #[inline(always)]
74 pub fn work_mode(&self) -> WORK_MODE_R {
75 WORK_MODE_R::new(((self.bits >> 3) & 3) as u8)
76 }
77 #[doc = "Bit 5 - 0: SAR1, 1: SAR2, only work for single SAR mode"]
78 #[inline(always)]
79 pub fn sar_sel(&self) -> SAR_SEL_R {
80 SAR_SEL_R::new(((self.bits >> 5) & 1) != 0)
81 }
82 #[doc = "Bit 6 - enable SAR CLK gate when saradc idle"]
83 #[inline(always)]
84 pub fn sar_clk_gated(&self) -> SAR_CLK_GATED_R {
85 SAR_CLK_GATED_R::new(((self.bits >> 6) & 1) != 0)
86 }
87 #[doc = "Bits 7:14 - SAR clock divider"]
88 #[inline(always)]
89 pub fn sar_clk_div(&self) -> SAR_CLK_DIV_R {
90 SAR_CLK_DIV_R::new(((self.bits >> 7) & 0xff) as u8)
91 }
92 #[doc = "Bits 15:18 - 0 ~ 15 means length 1 ~ 16"]
93 #[inline(always)]
94 pub fn sar1_patt_len(&self) -> SAR1_PATT_LEN_R {
95 SAR1_PATT_LEN_R::new(((self.bits >> 15) & 0x0f) as u8)
96 }
97 #[doc = "Bits 19:22 - 0 ~ 15 means length 1 ~ 16"]
98 #[inline(always)]
99 pub fn sar2_patt_len(&self) -> SAR2_PATT_LEN_R {
100 SAR2_PATT_LEN_R::new(((self.bits >> 19) & 0x0f) as u8)
101 }
102 #[doc = "Bit 23 - clear the pointer of pattern table for DIG ADC1 CTRL"]
103 #[inline(always)]
104 pub fn sar1_patt_p_clear(&self) -> SAR1_PATT_P_CLEAR_R {
105 SAR1_PATT_P_CLEAR_R::new(((self.bits >> 23) & 1) != 0)
106 }
107 #[doc = "Bit 24 - clear the pointer of pattern table for DIG ADC2 CTRL"]
108 #[inline(always)]
109 pub fn sar2_patt_p_clear(&self) -> SAR2_PATT_P_CLEAR_R {
110 SAR2_PATT_P_CLEAR_R::new(((self.bits >> 24) & 1) != 0)
111 }
112 #[doc = "Bit 25 - 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits."]
113 #[inline(always)]
114 pub fn data_sar_sel(&self) -> DATA_SAR_SEL_R {
115 DATA_SAR_SEL_R::new(((self.bits >> 25) & 1) != 0)
116 }
117 #[doc = "Bit 26 - 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix"]
118 #[inline(always)]
119 pub fn data_to_i2s(&self) -> DATA_TO_I2S_R {
120 DATA_TO_I2S_R::new(((self.bits >> 26) & 1) != 0)
121 }
122 #[doc = "Bits 27:28 - force option to xpd sar blocks"]
123 #[inline(always)]
124 pub fn xpd_sar_force(&self) -> XPD_SAR_FORCE_R {
125 XPD_SAR_FORCE_R::new(((self.bits >> 27) & 3) as u8)
126 }
127 #[doc = "Bits 30:31 - wait arbit signal stable after sar_done"]
128 #[inline(always)]
129 pub fn wait_arb_cycle(&self) -> WAIT_ARB_CYCLE_R {
130 WAIT_ARB_CYCLE_R::new(((self.bits >> 30) & 3) as u8)
131 }
132}
133#[cfg(feature = "impl-register-debug")]
134impl core::fmt::Debug for R {
135 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
136 f.debug_struct("CTRL")
137 .field("start_force", &self.start_force())
138 .field("start", &self.start())
139 .field("work_mode", &self.work_mode())
140 .field("sar_sel", &self.sar_sel())
141 .field("sar_clk_gated", &self.sar_clk_gated())
142 .field("sar_clk_div", &self.sar_clk_div())
143 .field("sar1_patt_len", &self.sar1_patt_len())
144 .field("sar2_patt_len", &self.sar2_patt_len())
145 .field("sar1_patt_p_clear", &self.sar1_patt_p_clear())
146 .field("sar2_patt_p_clear", &self.sar2_patt_p_clear())
147 .field("data_sar_sel", &self.data_sar_sel())
148 .field("data_to_i2s", &self.data_to_i2s())
149 .field("xpd_sar_force", &self.xpd_sar_force())
150 .field("wait_arb_cycle", &self.wait_arb_cycle())
151 .finish()
152 }
153}
154impl W {
155 #[doc = "Bit 0 - enable start saradc by sw"]
156 #[inline(always)]
157 pub fn start_force(&mut self) -> START_FORCE_W<CTRL_SPEC> {
158 START_FORCE_W::new(self, 0)
159 }
160 #[doc = "Bit 1 - start saradc by sw"]
161 #[inline(always)]
162 pub fn start(&mut self) -> START_W<CTRL_SPEC> {
163 START_W::new(self, 1)
164 }
165 #[doc = "Bits 3:4 - 0: single mode, 1: double mode, 2: alternate mode"]
166 #[inline(always)]
167 pub fn work_mode(&mut self) -> WORK_MODE_W<CTRL_SPEC> {
168 WORK_MODE_W::new(self, 3)
169 }
170 #[doc = "Bit 5 - 0: SAR1, 1: SAR2, only work for single SAR mode"]
171 #[inline(always)]
172 pub fn sar_sel(&mut self) -> SAR_SEL_W<CTRL_SPEC> {
173 SAR_SEL_W::new(self, 5)
174 }
175 #[doc = "Bit 6 - enable SAR CLK gate when saradc idle"]
176 #[inline(always)]
177 pub fn sar_clk_gated(&mut self) -> SAR_CLK_GATED_W<CTRL_SPEC> {
178 SAR_CLK_GATED_W::new(self, 6)
179 }
180 #[doc = "Bits 7:14 - SAR clock divider"]
181 #[inline(always)]
182 pub fn sar_clk_div(&mut self) -> SAR_CLK_DIV_W<CTRL_SPEC> {
183 SAR_CLK_DIV_W::new(self, 7)
184 }
185 #[doc = "Bits 15:18 - 0 ~ 15 means length 1 ~ 16"]
186 #[inline(always)]
187 pub fn sar1_patt_len(&mut self) -> SAR1_PATT_LEN_W<CTRL_SPEC> {
188 SAR1_PATT_LEN_W::new(self, 15)
189 }
190 #[doc = "Bits 19:22 - 0 ~ 15 means length 1 ~ 16"]
191 #[inline(always)]
192 pub fn sar2_patt_len(&mut self) -> SAR2_PATT_LEN_W<CTRL_SPEC> {
193 SAR2_PATT_LEN_W::new(self, 19)
194 }
195 #[doc = "Bit 23 - clear the pointer of pattern table for DIG ADC1 CTRL"]
196 #[inline(always)]
197 pub fn sar1_patt_p_clear(&mut self) -> SAR1_PATT_P_CLEAR_W<CTRL_SPEC> {
198 SAR1_PATT_P_CLEAR_W::new(self, 23)
199 }
200 #[doc = "Bit 24 - clear the pointer of pattern table for DIG ADC2 CTRL"]
201 #[inline(always)]
202 pub fn sar2_patt_p_clear(&mut self) -> SAR2_PATT_P_CLEAR_W<CTRL_SPEC> {
203 SAR2_PATT_P_CLEAR_W::new(self, 24)
204 }
205 #[doc = "Bit 25 - 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits."]
206 #[inline(always)]
207 pub fn data_sar_sel(&mut self) -> DATA_SAR_SEL_W<CTRL_SPEC> {
208 DATA_SAR_SEL_W::new(self, 25)
209 }
210 #[doc = "Bit 26 - 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix"]
211 #[inline(always)]
212 pub fn data_to_i2s(&mut self) -> DATA_TO_I2S_W<CTRL_SPEC> {
213 DATA_TO_I2S_W::new(self, 26)
214 }
215 #[doc = "Bits 27:28 - force option to xpd sar blocks"]
216 #[inline(always)]
217 pub fn xpd_sar_force(&mut self) -> XPD_SAR_FORCE_W<CTRL_SPEC> {
218 XPD_SAR_FORCE_W::new(self, 27)
219 }
220 #[doc = "Bits 30:31 - wait arbit signal stable after sar_done"]
221 #[inline(always)]
222 pub fn wait_arb_cycle(&mut self) -> WAIT_ARB_CYCLE_W<CTRL_SPEC> {
223 WAIT_ARB_CYCLE_W::new(self, 30)
224 }
225}
226#[doc = "configure apb saradc controller\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
227pub struct CTRL_SPEC;
228impl crate::RegisterSpec for CTRL_SPEC {
229 type Ux = u32;
230}
231#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
232impl crate::Readable for CTRL_SPEC {}
233#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
234impl crate::Writable for CTRL_SPEC {
235 type Safety = crate::Unsafe;
236}
237#[doc = "`reset()` method sets CTRL to value 0x407f_8240"]
238impl crate::Resettable for CTRL_SPEC {
239 const RESET_VALUE: u32 = 0x407f_8240;
240}