esp32s3/wcl/
core_1_message_phase.rs

1#[doc = "Register `Core_1_MESSAGE_PHASE` reader"]
2pub type R = crate::R<CORE_1_MESSAGE_PHASE_SPEC>;
3#[doc = "Field `CORE_1_MESSAGE_MATCH` reader - This bit indicates whether the check is successful"]
4pub type CORE_1_MESSAGE_MATCH_R = crate::BitReader;
5#[doc = "Field `CORE_1_MESSAGE_EXPECT` reader - This field indicates the data to be written next time"]
6pub type CORE_1_MESSAGE_EXPECT_R = crate::FieldReader;
7#[doc = "Field `CORE_1_MESSAGE_DATAPHASE` reader - If this bit is 1, it means that is checking clear write_buffer operation, and is checking data"]
8pub type CORE_1_MESSAGE_DATAPHASE_R = crate::BitReader;
9#[doc = "Field `CORE_1_MESSAGE_ADDRESSPHASE` reader - If this bit is 1, it means that is checking clear write_buffer operation, and is checking address."]
10pub type CORE_1_MESSAGE_ADDRESSPHASE_R = crate::BitReader;
11impl R {
12    #[doc = "Bit 0 - This bit indicates whether the check is successful"]
13    #[inline(always)]
14    pub fn core_1_message_match(&self) -> CORE_1_MESSAGE_MATCH_R {
15        CORE_1_MESSAGE_MATCH_R::new((self.bits & 1) != 0)
16    }
17    #[doc = "Bits 1:4 - This field indicates the data to be written next time"]
18    #[inline(always)]
19    pub fn core_1_message_expect(&self) -> CORE_1_MESSAGE_EXPECT_R {
20        CORE_1_MESSAGE_EXPECT_R::new(((self.bits >> 1) & 0x0f) as u8)
21    }
22    #[doc = "Bit 5 - If this bit is 1, it means that is checking clear write_buffer operation, and is checking data"]
23    #[inline(always)]
24    pub fn core_1_message_dataphase(&self) -> CORE_1_MESSAGE_DATAPHASE_R {
25        CORE_1_MESSAGE_DATAPHASE_R::new(((self.bits >> 5) & 1) != 0)
26    }
27    #[doc = "Bit 6 - If this bit is 1, it means that is checking clear write_buffer operation, and is checking address."]
28    #[inline(always)]
29    pub fn core_1_message_addressphase(&self) -> CORE_1_MESSAGE_ADDRESSPHASE_R {
30        CORE_1_MESSAGE_ADDRESSPHASE_R::new(((self.bits >> 6) & 1) != 0)
31    }
32}
33#[cfg(feature = "impl-register-debug")]
34impl core::fmt::Debug for R {
35    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
36        f.debug_struct("Core_1_MESSAGE_PHASE")
37            .field("core_1_message_match", &self.core_1_message_match())
38            .field("core_1_message_expect", &self.core_1_message_expect())
39            .field("core_1_message_dataphase", &self.core_1_message_dataphase())
40            .field(
41                "core_1_message_addressphase",
42                &self.core_1_message_addressphase(),
43            )
44            .finish()
45    }
46}
47#[doc = "Clear writer_buffer status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_message_phase::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
48pub struct CORE_1_MESSAGE_PHASE_SPEC;
49impl crate::RegisterSpec for CORE_1_MESSAGE_PHASE_SPEC {
50    type Ux = u32;
51}
52#[doc = "`read()` method returns [`core_1_message_phase::R`](R) reader structure"]
53impl crate::Readable for CORE_1_MESSAGE_PHASE_SPEC {}
54#[doc = "`reset()` method sets Core_1_MESSAGE_PHASE to value 0"]
55impl crate::Resettable for CORE_1_MESSAGE_PHASE_SPEC {
56    const RESET_VALUE: u32 = 0;
57}
esp32s3/wcl/core_1_message_phase.rs

esp32s3/wcl/
core_1_message_phase.rs
