1#[doc = "Register `DIN_MODE` reader"]
2pub type R = crate::R<DIN_MODE_SPEC>;
3#[doc = "Register `DIN_MODE` writer"]
4pub type W = crate::W<DIN_MODE_SPEC>;
5#[doc = "Field `DIN0_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
6pub type DIN0_MODE_R = crate::FieldReader;
7#[doc = "Field `DIN0_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
8pub type DIN0_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `DIN1_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
10pub type DIN1_MODE_R = crate::FieldReader;
11#[doc = "Field `DIN1_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
12pub type DIN1_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `DIN2_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
14pub type DIN2_MODE_R = crate::FieldReader;
15#[doc = "Field `DIN2_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
16pub type DIN2_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17#[doc = "Field `DIN3_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
18pub type DIN3_MODE_R = crate::FieldReader;
19#[doc = "Field `DIN3_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
20pub type DIN3_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21#[doc = "Field `DIN4_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
22pub type DIN4_MODE_R = crate::FieldReader;
23#[doc = "Field `DIN4_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
24pub type DIN4_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25#[doc = "Field `DIN5_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
26pub type DIN5_MODE_R = crate::FieldReader;
27#[doc = "Field `DIN5_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
28pub type DIN5_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29#[doc = "Field `DIN6_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
30pub type DIN6_MODE_R = crate::FieldReader;
31#[doc = "Field `DIN6_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
32pub type DIN6_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
33#[doc = "Field `DIN7_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
34pub type DIN7_MODE_R = crate::FieldReader;
35#[doc = "Field `DIN7_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
36pub type DIN7_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
37#[doc = "Field `TIMING_HCLK_ACTIVE` reader - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state."]
38pub type TIMING_HCLK_ACTIVE_R = crate::BitReader;
39#[doc = "Field `TIMING_HCLK_ACTIVE` writer - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state."]
40pub type TIMING_HCLK_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
41impl R {
42 #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
43 #[inline(always)]
44 pub fn din0_mode(&self) -> DIN0_MODE_R {
45 DIN0_MODE_R::new((self.bits & 3) as u8)
46 }
47 #[doc = "Bits 2:3 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
48 #[inline(always)]
49 pub fn din1_mode(&self) -> DIN1_MODE_R {
50 DIN1_MODE_R::new(((self.bits >> 2) & 3) as u8)
51 }
52 #[doc = "Bits 4:5 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
53 #[inline(always)]
54 pub fn din2_mode(&self) -> DIN2_MODE_R {
55 DIN2_MODE_R::new(((self.bits >> 4) & 3) as u8)
56 }
57 #[doc = "Bits 6:7 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
58 #[inline(always)]
59 pub fn din3_mode(&self) -> DIN3_MODE_R {
60 DIN3_MODE_R::new(((self.bits >> 6) & 3) as u8)
61 }
62 #[doc = "Bits 8:9 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
63 #[inline(always)]
64 pub fn din4_mode(&self) -> DIN4_MODE_R {
65 DIN4_MODE_R::new(((self.bits >> 8) & 3) as u8)
66 }
67 #[doc = "Bits 10:11 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
68 #[inline(always)]
69 pub fn din5_mode(&self) -> DIN5_MODE_R {
70 DIN5_MODE_R::new(((self.bits >> 10) & 3) as u8)
71 }
72 #[doc = "Bits 12:13 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
73 #[inline(always)]
74 pub fn din6_mode(&self) -> DIN6_MODE_R {
75 DIN6_MODE_R::new(((self.bits >> 12) & 3) as u8)
76 }
77 #[doc = "Bits 14:15 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
78 #[inline(always)]
79 pub fn din7_mode(&self) -> DIN7_MODE_R {
80 DIN7_MODE_R::new(((self.bits >> 14) & 3) as u8)
81 }
82 #[doc = "Bit 16 - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state."]
83 #[inline(always)]
84 pub fn timing_hclk_active(&self) -> TIMING_HCLK_ACTIVE_R {
85 TIMING_HCLK_ACTIVE_R::new(((self.bits >> 16) & 1) != 0)
86 }
87}
88#[cfg(feature = "impl-register-debug")]
89impl core::fmt::Debug for R {
90 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
91 f.debug_struct("DIN_MODE")
92 .field("din0_mode", &self.din0_mode())
93 .field("din1_mode", &self.din1_mode())
94 .field("din2_mode", &self.din2_mode())
95 .field("din3_mode", &self.din3_mode())
96 .field("din4_mode", &self.din4_mode())
97 .field("din5_mode", &self.din5_mode())
98 .field("din6_mode", &self.din6_mode())
99 .field("din7_mode", &self.din7_mode())
100 .field("timing_hclk_active", &self.timing_hclk_active())
101 .finish()
102 }
103}
104impl W {
105 #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
106 #[inline(always)]
107 pub fn din0_mode(&mut self) -> DIN0_MODE_W<DIN_MODE_SPEC> {
108 DIN0_MODE_W::new(self, 0)
109 }
110 #[doc = "Bits 2:3 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
111 #[inline(always)]
112 pub fn din1_mode(&mut self) -> DIN1_MODE_W<DIN_MODE_SPEC> {
113 DIN1_MODE_W::new(self, 2)
114 }
115 #[doc = "Bits 4:5 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
116 #[inline(always)]
117 pub fn din2_mode(&mut self) -> DIN2_MODE_W<DIN_MODE_SPEC> {
118 DIN2_MODE_W::new(self, 4)
119 }
120 #[doc = "Bits 6:7 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
121 #[inline(always)]
122 pub fn din3_mode(&mut self) -> DIN3_MODE_W<DIN_MODE_SPEC> {
123 DIN3_MODE_W::new(self, 6)
124 }
125 #[doc = "Bits 8:9 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
126 #[inline(always)]
127 pub fn din4_mode(&mut self) -> DIN4_MODE_W<DIN_MODE_SPEC> {
128 DIN4_MODE_W::new(self, 8)
129 }
130 #[doc = "Bits 10:11 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
131 #[inline(always)]
132 pub fn din5_mode(&mut self) -> DIN5_MODE_W<DIN_MODE_SPEC> {
133 DIN5_MODE_W::new(self, 10)
134 }
135 #[doc = "Bits 12:13 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
136 #[inline(always)]
137 pub fn din6_mode(&mut self) -> DIN6_MODE_W<DIN_MODE_SPEC> {
138 DIN6_MODE_W::new(self, 12)
139 }
140 #[doc = "Bits 14:15 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
141 #[inline(always)]
142 pub fn din7_mode(&mut self) -> DIN7_MODE_W<DIN_MODE_SPEC> {
143 DIN7_MODE_W::new(self, 14)
144 }
145 #[doc = "Bit 16 - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state."]
146 #[inline(always)]
147 pub fn timing_hclk_active(&mut self) -> TIMING_HCLK_ACTIVE_W<DIN_MODE_SPEC> {
148 TIMING_HCLK_ACTIVE_W::new(self, 16)
149 }
150}
151#[doc = "SPI input delay mode configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`din_mode::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`din_mode::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
152pub struct DIN_MODE_SPEC;
153impl crate::RegisterSpec for DIN_MODE_SPEC {
154 type Ux = u32;
155}
156#[doc = "`read()` method returns [`din_mode::R`](R) reader structure"]
157impl crate::Readable for DIN_MODE_SPEC {}
158#[doc = "`write(|w| ..)` method takes [`din_mode::W`](W) writer structure"]
159impl crate::Writable for DIN_MODE_SPEC {
160 type Safety = crate::Unsafe;
161 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
162 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
163}
164#[doc = "`reset()` method sets DIN_MODE to value 0"]
165impl crate::Resettable for DIN_MODE_SPEC {
166 const RESET_VALUE: u32 = 0;
167}