1#[doc = "Register `DDR` reader"]
2pub type R = crate::R<DDR_SPEC>;
3#[doc = "Register `DDR` writer"]
4pub type W = crate::W<DDR_SPEC>;
5#[doc = "Field `SPI_FMEM_DDR_EN` reader - 1: in ddr mode, 0 in sdr mode"]
6pub type SPI_FMEM_DDR_EN_R = crate::BitReader;
7#[doc = "Field `SPI_FMEM_DDR_EN` writer - 1: in ddr mode, 0 in sdr mode"]
8pub type SPI_FMEM_DDR_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SPI_FMEM_VAR_DUMMY` reader - Set the bit to enable variable dummy cycle in DDR mode."]
10pub type SPI_FMEM_VAR_DUMMY_R = crate::BitReader;
11#[doc = "Field `SPI_FMEM_VAR_DUMMY` writer - Set the bit to enable variable dummy cycle in DDR mode."]
12pub type SPI_FMEM_VAR_DUMMY_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SPI_FMEM_DDR_RDAT_SWP` reader - Set the bit to reorder RX data of the word in DDR mode."]
14pub type SPI_FMEM_DDR_RDAT_SWP_R = crate::BitReader;
15#[doc = "Field `SPI_FMEM_DDR_RDAT_SWP` writer - Set the bit to reorder RX data of the word in DDR mode."]
16pub type SPI_FMEM_DDR_RDAT_SWP_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SPI_FMEM_DDR_WDAT_SWP` reader - Set the bit to swap TX data of a word in DDR mode."]
18pub type SPI_FMEM_DDR_WDAT_SWP_R = crate::BitReader;
19#[doc = "Field `SPI_FMEM_DDR_WDAT_SWP` writer - Set the bit to swap TX data of a word in DDR mode."]
20pub type SPI_FMEM_DDR_WDAT_SWP_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `SPI_FMEM_DDR_CMD_DIS` reader - the bit is used to disable dual edge in CMD phase when ddr mode."]
22pub type SPI_FMEM_DDR_CMD_DIS_R = crate::BitReader;
23#[doc = "Field `SPI_FMEM_DDR_CMD_DIS` writer - the bit is used to disable dual edge in CMD phase when ddr mode."]
24pub type SPI_FMEM_DDR_CMD_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `SPI_FMEM_OUTMINBYTELEN` reader - It is the minimum output data length in the panda device."]
26pub type SPI_FMEM_OUTMINBYTELEN_R = crate::FieldReader;
27#[doc = "Field `SPI_FMEM_OUTMINBYTELEN` writer - It is the minimum output data length in the panda device."]
28pub type SPI_FMEM_OUTMINBYTELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
29#[doc = "Field `SPI_FMEM_TX_DDR_MSK_EN` reader - Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to flash."]
30pub type SPI_FMEM_TX_DDR_MSK_EN_R = crate::BitReader;
31#[doc = "Field `SPI_FMEM_TX_DDR_MSK_EN` writer - Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to flash."]
32pub type SPI_FMEM_TX_DDR_MSK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `SPI_FMEM_RX_DDR_MSK_EN` reader - Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to flash."]
34pub type SPI_FMEM_RX_DDR_MSK_EN_R = crate::BitReader;
35#[doc = "Field `SPI_FMEM_RX_DDR_MSK_EN` writer - Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to flash."]
36pub type SPI_FMEM_RX_DDR_MSK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `SPI_FMEM_USR_DDR_DQS_THD` reader - The delay number of data strobe which from memory based on SPI_CLK."]
38pub type SPI_FMEM_USR_DDR_DQS_THD_R = crate::FieldReader;
39#[doc = "Field `SPI_FMEM_USR_DDR_DQS_THD` writer - The delay number of data strobe which from memory based on SPI_CLK."]
40pub type SPI_FMEM_USR_DDR_DQS_THD_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
41#[doc = "Field `SPI_FMEM_DDR_DQS_LOOP` reader - 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module"]
42pub type SPI_FMEM_DDR_DQS_LOOP_R = crate::BitReader;
43#[doc = "Field `SPI_FMEM_DDR_DQS_LOOP` writer - 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module"]
44pub type SPI_FMEM_DDR_DQS_LOOP_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `SPI_FMEM_DDR_DQS_LOOP_MODE` reader - When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active."]
46pub type SPI_FMEM_DDR_DQS_LOOP_MODE_R = crate::BitReader;
47#[doc = "Field `SPI_FMEM_DDR_DQS_LOOP_MODE` writer - When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active."]
48pub type SPI_FMEM_DDR_DQS_LOOP_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `SPI_FMEM_CLK_DIFF_EN` reader - Set this bit to enable the differential SPI_CLK#."]
50pub type SPI_FMEM_CLK_DIFF_EN_R = crate::BitReader;
51#[doc = "Field `SPI_FMEM_CLK_DIFF_EN` writer - Set this bit to enable the differential SPI_CLK#."]
52pub type SPI_FMEM_CLK_DIFF_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `SPI_FMEM_HYPERBUS_MODE` reader - Set this bit to enable the SPI HyperBus mode."]
54pub type SPI_FMEM_HYPERBUS_MODE_R = crate::BitReader;
55#[doc = "Field `SPI_FMEM_HYPERBUS_MODE` writer - Set this bit to enable the SPI HyperBus mode."]
56pub type SPI_FMEM_HYPERBUS_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `SPI_FMEM_DQS_CA_IN` reader - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR."]
58pub type SPI_FMEM_DQS_CA_IN_R = crate::BitReader;
59#[doc = "Field `SPI_FMEM_DQS_CA_IN` writer - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR."]
60pub type SPI_FMEM_DQS_CA_IN_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `SPI_FMEM_HYPERBUS_DUMMY_2X` reader - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram."]
62pub type SPI_FMEM_HYPERBUS_DUMMY_2X_R = crate::BitReader;
63#[doc = "Field `SPI_FMEM_HYPERBUS_DUMMY_2X` writer - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram."]
64pub type SPI_FMEM_HYPERBUS_DUMMY_2X_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `SPI_FMEM_CLK_DIFF_INV` reader - Set this bit to invert SPI_DIFF when accesses to flash. ."]
66pub type SPI_FMEM_CLK_DIFF_INV_R = crate::BitReader;
67#[doc = "Field `SPI_FMEM_CLK_DIFF_INV` writer - Set this bit to invert SPI_DIFF when accesses to flash. ."]
68pub type SPI_FMEM_CLK_DIFF_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `SPI_FMEM_OCTA_RAM_ADDR` reader - Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[25:4\\], 6'd0, spi_usr_addr_value\\[3:1\\], 1'b0}."]
70pub type SPI_FMEM_OCTA_RAM_ADDR_R = crate::BitReader;
71#[doc = "Field `SPI_FMEM_OCTA_RAM_ADDR` writer - Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[25:4\\], 6'd0, spi_usr_addr_value\\[3:1\\], 1'b0}."]
72pub type SPI_FMEM_OCTA_RAM_ADDR_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `SPI_FMEM_HYPERBUS_CA` reader - Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[19:4\\], 13'd0, spi_usr_addr_value\\[3:1\\]}."]
74pub type SPI_FMEM_HYPERBUS_CA_R = crate::BitReader;
75#[doc = "Field `SPI_FMEM_HYPERBUS_CA` writer - Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[19:4\\], 13'd0, spi_usr_addr_value\\[3:1\\]}."]
76pub type SPI_FMEM_HYPERBUS_CA_W<'a, REG> = crate::BitWriter<'a, REG>;
77impl R {
78 #[doc = "Bit 0 - 1: in ddr mode, 0 in sdr mode"]
79 #[inline(always)]
80 pub fn spi_fmem_ddr_en(&self) -> SPI_FMEM_DDR_EN_R {
81 SPI_FMEM_DDR_EN_R::new((self.bits & 1) != 0)
82 }
83 #[doc = "Bit 1 - Set the bit to enable variable dummy cycle in DDR mode."]
84 #[inline(always)]
85 pub fn spi_fmem_var_dummy(&self) -> SPI_FMEM_VAR_DUMMY_R {
86 SPI_FMEM_VAR_DUMMY_R::new(((self.bits >> 1) & 1) != 0)
87 }
88 #[doc = "Bit 2 - Set the bit to reorder RX data of the word in DDR mode."]
89 #[inline(always)]
90 pub fn spi_fmem_ddr_rdat_swp(&self) -> SPI_FMEM_DDR_RDAT_SWP_R {
91 SPI_FMEM_DDR_RDAT_SWP_R::new(((self.bits >> 2) & 1) != 0)
92 }
93 #[doc = "Bit 3 - Set the bit to swap TX data of a word in DDR mode."]
94 #[inline(always)]
95 pub fn spi_fmem_ddr_wdat_swp(&self) -> SPI_FMEM_DDR_WDAT_SWP_R {
96 SPI_FMEM_DDR_WDAT_SWP_R::new(((self.bits >> 3) & 1) != 0)
97 }
98 #[doc = "Bit 4 - the bit is used to disable dual edge in CMD phase when ddr mode."]
99 #[inline(always)]
100 pub fn spi_fmem_ddr_cmd_dis(&self) -> SPI_FMEM_DDR_CMD_DIS_R {
101 SPI_FMEM_DDR_CMD_DIS_R::new(((self.bits >> 4) & 1) != 0)
102 }
103 #[doc = "Bits 5:11 - It is the minimum output data length in the panda device."]
104 #[inline(always)]
105 pub fn spi_fmem_outminbytelen(&self) -> SPI_FMEM_OUTMINBYTELEN_R {
106 SPI_FMEM_OUTMINBYTELEN_R::new(((self.bits >> 5) & 0x7f) as u8)
107 }
108 #[doc = "Bit 12 - Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to flash."]
109 #[inline(always)]
110 pub fn spi_fmem_tx_ddr_msk_en(&self) -> SPI_FMEM_TX_DDR_MSK_EN_R {
111 SPI_FMEM_TX_DDR_MSK_EN_R::new(((self.bits >> 12) & 1) != 0)
112 }
113 #[doc = "Bit 13 - Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to flash."]
114 #[inline(always)]
115 pub fn spi_fmem_rx_ddr_msk_en(&self) -> SPI_FMEM_RX_DDR_MSK_EN_R {
116 SPI_FMEM_RX_DDR_MSK_EN_R::new(((self.bits >> 13) & 1) != 0)
117 }
118 #[doc = "Bits 14:20 - The delay number of data strobe which from memory based on SPI_CLK."]
119 #[inline(always)]
120 pub fn spi_fmem_usr_ddr_dqs_thd(&self) -> SPI_FMEM_USR_DDR_DQS_THD_R {
121 SPI_FMEM_USR_DDR_DQS_THD_R::new(((self.bits >> 14) & 0x7f) as u8)
122 }
123 #[doc = "Bit 21 - 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module"]
124 #[inline(always)]
125 pub fn spi_fmem_ddr_dqs_loop(&self) -> SPI_FMEM_DDR_DQS_LOOP_R {
126 SPI_FMEM_DDR_DQS_LOOP_R::new(((self.bits >> 21) & 1) != 0)
127 }
128 #[doc = "Bit 22 - When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active."]
129 #[inline(always)]
130 pub fn spi_fmem_ddr_dqs_loop_mode(&self) -> SPI_FMEM_DDR_DQS_LOOP_MODE_R {
131 SPI_FMEM_DDR_DQS_LOOP_MODE_R::new(((self.bits >> 22) & 1) != 0)
132 }
133 #[doc = "Bit 24 - Set this bit to enable the differential SPI_CLK#."]
134 #[inline(always)]
135 pub fn spi_fmem_clk_diff_en(&self) -> SPI_FMEM_CLK_DIFF_EN_R {
136 SPI_FMEM_CLK_DIFF_EN_R::new(((self.bits >> 24) & 1) != 0)
137 }
138 #[doc = "Bit 25 - Set this bit to enable the SPI HyperBus mode."]
139 #[inline(always)]
140 pub fn spi_fmem_hyperbus_mode(&self) -> SPI_FMEM_HYPERBUS_MODE_R {
141 SPI_FMEM_HYPERBUS_MODE_R::new(((self.bits >> 25) & 1) != 0)
142 }
143 #[doc = "Bit 26 - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR."]
144 #[inline(always)]
145 pub fn spi_fmem_dqs_ca_in(&self) -> SPI_FMEM_DQS_CA_IN_R {
146 SPI_FMEM_DQS_CA_IN_R::new(((self.bits >> 26) & 1) != 0)
147 }
148 #[doc = "Bit 27 - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram."]
149 #[inline(always)]
150 pub fn spi_fmem_hyperbus_dummy_2x(&self) -> SPI_FMEM_HYPERBUS_DUMMY_2X_R {
151 SPI_FMEM_HYPERBUS_DUMMY_2X_R::new(((self.bits >> 27) & 1) != 0)
152 }
153 #[doc = "Bit 28 - Set this bit to invert SPI_DIFF when accesses to flash. ."]
154 #[inline(always)]
155 pub fn spi_fmem_clk_diff_inv(&self) -> SPI_FMEM_CLK_DIFF_INV_R {
156 SPI_FMEM_CLK_DIFF_INV_R::new(((self.bits >> 28) & 1) != 0)
157 }
158 #[doc = "Bit 29 - Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[25:4\\], 6'd0, spi_usr_addr_value\\[3:1\\], 1'b0}."]
159 #[inline(always)]
160 pub fn spi_fmem_octa_ram_addr(&self) -> SPI_FMEM_OCTA_RAM_ADDR_R {
161 SPI_FMEM_OCTA_RAM_ADDR_R::new(((self.bits >> 29) & 1) != 0)
162 }
163 #[doc = "Bit 30 - Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[19:4\\], 13'd0, spi_usr_addr_value\\[3:1\\]}."]
164 #[inline(always)]
165 pub fn spi_fmem_hyperbus_ca(&self) -> SPI_FMEM_HYPERBUS_CA_R {
166 SPI_FMEM_HYPERBUS_CA_R::new(((self.bits >> 30) & 1) != 0)
167 }
168}
169#[cfg(feature = "impl-register-debug")]
170impl core::fmt::Debug for R {
171 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
172 f.debug_struct("DDR")
173 .field("spi_fmem_ddr_en", &self.spi_fmem_ddr_en())
174 .field("spi_fmem_var_dummy", &self.spi_fmem_var_dummy())
175 .field("spi_fmem_ddr_rdat_swp", &self.spi_fmem_ddr_rdat_swp())
176 .field("spi_fmem_ddr_wdat_swp", &self.spi_fmem_ddr_wdat_swp())
177 .field("spi_fmem_ddr_cmd_dis", &self.spi_fmem_ddr_cmd_dis())
178 .field("spi_fmem_outminbytelen", &self.spi_fmem_outminbytelen())
179 .field("spi_fmem_tx_ddr_msk_en", &self.spi_fmem_tx_ddr_msk_en())
180 .field("spi_fmem_rx_ddr_msk_en", &self.spi_fmem_rx_ddr_msk_en())
181 .field("spi_fmem_usr_ddr_dqs_thd", &self.spi_fmem_usr_ddr_dqs_thd())
182 .field("spi_fmem_ddr_dqs_loop", &self.spi_fmem_ddr_dqs_loop())
183 .field(
184 "spi_fmem_ddr_dqs_loop_mode",
185 &self.spi_fmem_ddr_dqs_loop_mode(),
186 )
187 .field("spi_fmem_clk_diff_en", &self.spi_fmem_clk_diff_en())
188 .field("spi_fmem_hyperbus_mode", &self.spi_fmem_hyperbus_mode())
189 .field("spi_fmem_dqs_ca_in", &self.spi_fmem_dqs_ca_in())
190 .field(
191 "spi_fmem_hyperbus_dummy_2x",
192 &self.spi_fmem_hyperbus_dummy_2x(),
193 )
194 .field("spi_fmem_clk_diff_inv", &self.spi_fmem_clk_diff_inv())
195 .field("spi_fmem_octa_ram_addr", &self.spi_fmem_octa_ram_addr())
196 .field("spi_fmem_hyperbus_ca", &self.spi_fmem_hyperbus_ca())
197 .finish()
198 }
199}
200impl W {
201 #[doc = "Bit 0 - 1: in ddr mode, 0 in sdr mode"]
202 #[inline(always)]
203 pub fn spi_fmem_ddr_en(&mut self) -> SPI_FMEM_DDR_EN_W<DDR_SPEC> {
204 SPI_FMEM_DDR_EN_W::new(self, 0)
205 }
206 #[doc = "Bit 1 - Set the bit to enable variable dummy cycle in DDR mode."]
207 #[inline(always)]
208 pub fn spi_fmem_var_dummy(&mut self) -> SPI_FMEM_VAR_DUMMY_W<DDR_SPEC> {
209 SPI_FMEM_VAR_DUMMY_W::new(self, 1)
210 }
211 #[doc = "Bit 2 - Set the bit to reorder RX data of the word in DDR mode."]
212 #[inline(always)]
213 pub fn spi_fmem_ddr_rdat_swp(&mut self) -> SPI_FMEM_DDR_RDAT_SWP_W<DDR_SPEC> {
214 SPI_FMEM_DDR_RDAT_SWP_W::new(self, 2)
215 }
216 #[doc = "Bit 3 - Set the bit to swap TX data of a word in DDR mode."]
217 #[inline(always)]
218 pub fn spi_fmem_ddr_wdat_swp(&mut self) -> SPI_FMEM_DDR_WDAT_SWP_W<DDR_SPEC> {
219 SPI_FMEM_DDR_WDAT_SWP_W::new(self, 3)
220 }
221 #[doc = "Bit 4 - the bit is used to disable dual edge in CMD phase when ddr mode."]
222 #[inline(always)]
223 pub fn spi_fmem_ddr_cmd_dis(&mut self) -> SPI_FMEM_DDR_CMD_DIS_W<DDR_SPEC> {
224 SPI_FMEM_DDR_CMD_DIS_W::new(self, 4)
225 }
226 #[doc = "Bits 5:11 - It is the minimum output data length in the panda device."]
227 #[inline(always)]
228 pub fn spi_fmem_outminbytelen(&mut self) -> SPI_FMEM_OUTMINBYTELEN_W<DDR_SPEC> {
229 SPI_FMEM_OUTMINBYTELEN_W::new(self, 5)
230 }
231 #[doc = "Bit 12 - Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to flash."]
232 #[inline(always)]
233 pub fn spi_fmem_tx_ddr_msk_en(&mut self) -> SPI_FMEM_TX_DDR_MSK_EN_W<DDR_SPEC> {
234 SPI_FMEM_TX_DDR_MSK_EN_W::new(self, 12)
235 }
236 #[doc = "Bit 13 - Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to flash."]
237 #[inline(always)]
238 pub fn spi_fmem_rx_ddr_msk_en(&mut self) -> SPI_FMEM_RX_DDR_MSK_EN_W<DDR_SPEC> {
239 SPI_FMEM_RX_DDR_MSK_EN_W::new(self, 13)
240 }
241 #[doc = "Bits 14:20 - The delay number of data strobe which from memory based on SPI_CLK."]
242 #[inline(always)]
243 pub fn spi_fmem_usr_ddr_dqs_thd(&mut self) -> SPI_FMEM_USR_DDR_DQS_THD_W<DDR_SPEC> {
244 SPI_FMEM_USR_DDR_DQS_THD_W::new(self, 14)
245 }
246 #[doc = "Bit 21 - 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module"]
247 #[inline(always)]
248 pub fn spi_fmem_ddr_dqs_loop(&mut self) -> SPI_FMEM_DDR_DQS_LOOP_W<DDR_SPEC> {
249 SPI_FMEM_DDR_DQS_LOOP_W::new(self, 21)
250 }
251 #[doc = "Bit 22 - When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active."]
252 #[inline(always)]
253 pub fn spi_fmem_ddr_dqs_loop_mode(&mut self) -> SPI_FMEM_DDR_DQS_LOOP_MODE_W<DDR_SPEC> {
254 SPI_FMEM_DDR_DQS_LOOP_MODE_W::new(self, 22)
255 }
256 #[doc = "Bit 24 - Set this bit to enable the differential SPI_CLK#."]
257 #[inline(always)]
258 pub fn spi_fmem_clk_diff_en(&mut self) -> SPI_FMEM_CLK_DIFF_EN_W<DDR_SPEC> {
259 SPI_FMEM_CLK_DIFF_EN_W::new(self, 24)
260 }
261 #[doc = "Bit 25 - Set this bit to enable the SPI HyperBus mode."]
262 #[inline(always)]
263 pub fn spi_fmem_hyperbus_mode(&mut self) -> SPI_FMEM_HYPERBUS_MODE_W<DDR_SPEC> {
264 SPI_FMEM_HYPERBUS_MODE_W::new(self, 25)
265 }
266 #[doc = "Bit 26 - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR."]
267 #[inline(always)]
268 pub fn spi_fmem_dqs_ca_in(&mut self) -> SPI_FMEM_DQS_CA_IN_W<DDR_SPEC> {
269 SPI_FMEM_DQS_CA_IN_W::new(self, 26)
270 }
271 #[doc = "Bit 27 - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram."]
272 #[inline(always)]
273 pub fn spi_fmem_hyperbus_dummy_2x(&mut self) -> SPI_FMEM_HYPERBUS_DUMMY_2X_W<DDR_SPEC> {
274 SPI_FMEM_HYPERBUS_DUMMY_2X_W::new(self, 27)
275 }
276 #[doc = "Bit 28 - Set this bit to invert SPI_DIFF when accesses to flash. ."]
277 #[inline(always)]
278 pub fn spi_fmem_clk_diff_inv(&mut self) -> SPI_FMEM_CLK_DIFF_INV_W<DDR_SPEC> {
279 SPI_FMEM_CLK_DIFF_INV_W::new(self, 28)
280 }
281 #[doc = "Bit 29 - Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[25:4\\], 6'd0, spi_usr_addr_value\\[3:1\\], 1'b0}."]
282 #[inline(always)]
283 pub fn spi_fmem_octa_ram_addr(&mut self) -> SPI_FMEM_OCTA_RAM_ADDR_W<DDR_SPEC> {
284 SPI_FMEM_OCTA_RAM_ADDR_W::new(self, 29)
285 }
286 #[doc = "Bit 30 - Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[19:4\\], 13'd0, spi_usr_addr_value\\[3:1\\]}."]
287 #[inline(always)]
288 pub fn spi_fmem_hyperbus_ca(&mut self) -> SPI_FMEM_HYPERBUS_CA_W<DDR_SPEC> {
289 SPI_FMEM_HYPERBUS_CA_W::new(self, 30)
290 }
291}
292#[doc = "SPI0 flash DDR mode control register\n\nYou can [`read`](crate::Reg::read) this register and get [`ddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
293pub struct DDR_SPEC;
294impl crate::RegisterSpec for DDR_SPEC {
295 type Ux = u32;
296}
297#[doc = "`read()` method returns [`ddr::R`](R) reader structure"]
298impl crate::Readable for DDR_SPEC {}
299#[doc = "`write(|w| ..)` method takes [`ddr::W`](W) writer structure"]
300impl crate::Writable for DDR_SPEC {
301 type Safety = crate::Unsafe;
302 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
303 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
304}
305#[doc = "`reset()` method sets DDR to value 0x3020"]
306impl crate::Resettable for DDR_SPEC {
307 const RESET_VALUE: u32 = 0x3020;
308}