1#[doc = "Register `CTRL2` reader"]
2pub type R = crate::R<CTRL2_SPEC>;
3#[doc = "Register `CTRL2` writer"]
4pub type W = crate::W<CTRL2_SPEC>;
5#[doc = "Field `CS_SETUP_TIME` reader - (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit."]
6pub type CS_SETUP_TIME_R = crate::FieldReader;
7#[doc = "Field `CS_SETUP_TIME` writer - (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit."]
8pub type CS_SETUP_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Field `CS_HOLD_TIME` reader - SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit."]
10pub type CS_HOLD_TIME_R = crate::FieldReader;
11#[doc = "Field `CS_HOLD_TIME` writer - SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit."]
12pub type CS_HOLD_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
13#[doc = "Field `ECC_CS_HOLD_TIME` reader - SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI_CS hold cycle in ECC mode when accessed flash."]
14pub type ECC_CS_HOLD_TIME_R = crate::FieldReader;
15#[doc = "Field `ECC_CS_HOLD_TIME` writer - SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI_CS hold cycle in ECC mode when accessed flash."]
16pub type ECC_CS_HOLD_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17#[doc = "Field `ECC_SKIP_PAGE_CORNER` reader - 1: MSPI skips page corner when accesses flash. 0: Not skip page corner when accesses flash."]
18pub type ECC_SKIP_PAGE_CORNER_R = crate::BitReader;
19#[doc = "Field `ECC_SKIP_PAGE_CORNER` writer - 1: MSPI skips page corner when accesses flash. 0: Not skip page corner when accesses flash."]
20pub type ECC_SKIP_PAGE_CORNER_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `ECC_16TO18_BYTE_EN` reader - Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses flash."]
22pub type ECC_16TO18_BYTE_EN_R = crate::BitReader;
23#[doc = "Field `ECC_16TO18_BYTE_EN` writer - Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses flash."]
24pub type ECC_16TO18_BYTE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `CS_HOLD_DELAY` reader - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY\\[5:0\\] + 1) MSPI core clock cycles."]
26pub type CS_HOLD_DELAY_R = crate::FieldReader;
27#[doc = "Field `CS_HOLD_DELAY` writer - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY\\[5:0\\] + 1) MSPI core clock cycles."]
28pub type CS_HOLD_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
29#[doc = "Field `SYNC_RESET` reader - The FSM will be reset."]
30pub type SYNC_RESET_R = crate::BitReader;
31#[doc = "Field `SYNC_RESET` writer - The FSM will be reset."]
32pub type SYNC_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
33impl R {
34 #[doc = "Bits 0:4 - (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit."]
35 #[inline(always)]
36 pub fn cs_setup_time(&self) -> CS_SETUP_TIME_R {
37 CS_SETUP_TIME_R::new((self.bits & 0x1f) as u8)
38 }
39 #[doc = "Bits 5:9 - SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit."]
40 #[inline(always)]
41 pub fn cs_hold_time(&self) -> CS_HOLD_TIME_R {
42 CS_HOLD_TIME_R::new(((self.bits >> 5) & 0x1f) as u8)
43 }
44 #[doc = "Bits 10:12 - SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI_CS hold cycle in ECC mode when accessed flash."]
45 #[inline(always)]
46 pub fn ecc_cs_hold_time(&self) -> ECC_CS_HOLD_TIME_R {
47 ECC_CS_HOLD_TIME_R::new(((self.bits >> 10) & 7) as u8)
48 }
49 #[doc = "Bit 13 - 1: MSPI skips page corner when accesses flash. 0: Not skip page corner when accesses flash."]
50 #[inline(always)]
51 pub fn ecc_skip_page_corner(&self) -> ECC_SKIP_PAGE_CORNER_R {
52 ECC_SKIP_PAGE_CORNER_R::new(((self.bits >> 13) & 1) != 0)
53 }
54 #[doc = "Bit 14 - Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses flash."]
55 #[inline(always)]
56 pub fn ecc_16to18_byte_en(&self) -> ECC_16TO18_BYTE_EN_R {
57 ECC_16TO18_BYTE_EN_R::new(((self.bits >> 14) & 1) != 0)
58 }
59 #[doc = "Bits 25:30 - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY\\[5:0\\] + 1) MSPI core clock cycles."]
60 #[inline(always)]
61 pub fn cs_hold_delay(&self) -> CS_HOLD_DELAY_R {
62 CS_HOLD_DELAY_R::new(((self.bits >> 25) & 0x3f) as u8)
63 }
64 #[doc = "Bit 31 - The FSM will be reset."]
65 #[inline(always)]
66 pub fn sync_reset(&self) -> SYNC_RESET_R {
67 SYNC_RESET_R::new(((self.bits >> 31) & 1) != 0)
68 }
69}
70#[cfg(feature = "impl-register-debug")]
71impl core::fmt::Debug for R {
72 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
73 f.debug_struct("CTRL2")
74 .field("cs_setup_time", &self.cs_setup_time())
75 .field("cs_hold_time", &self.cs_hold_time())
76 .field("ecc_cs_hold_time", &self.ecc_cs_hold_time())
77 .field("ecc_skip_page_corner", &self.ecc_skip_page_corner())
78 .field("ecc_16to18_byte_en", &self.ecc_16to18_byte_en())
79 .field("cs_hold_delay", &self.cs_hold_delay())
80 .field("sync_reset", &self.sync_reset())
81 .finish()
82 }
83}
84impl W {
85 #[doc = "Bits 0:4 - (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit."]
86 #[inline(always)]
87 pub fn cs_setup_time(&mut self) -> CS_SETUP_TIME_W<CTRL2_SPEC> {
88 CS_SETUP_TIME_W::new(self, 0)
89 }
90 #[doc = "Bits 5:9 - SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit."]
91 #[inline(always)]
92 pub fn cs_hold_time(&mut self) -> CS_HOLD_TIME_W<CTRL2_SPEC> {
93 CS_HOLD_TIME_W::new(self, 5)
94 }
95 #[doc = "Bits 10:12 - SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI_CS hold cycle in ECC mode when accessed flash."]
96 #[inline(always)]
97 pub fn ecc_cs_hold_time(&mut self) -> ECC_CS_HOLD_TIME_W<CTRL2_SPEC> {
98 ECC_CS_HOLD_TIME_W::new(self, 10)
99 }
100 #[doc = "Bit 13 - 1: MSPI skips page corner when accesses flash. 0: Not skip page corner when accesses flash."]
101 #[inline(always)]
102 pub fn ecc_skip_page_corner(&mut self) -> ECC_SKIP_PAGE_CORNER_W<CTRL2_SPEC> {
103 ECC_SKIP_PAGE_CORNER_W::new(self, 13)
104 }
105 #[doc = "Bit 14 - Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses flash."]
106 #[inline(always)]
107 pub fn ecc_16to18_byte_en(&mut self) -> ECC_16TO18_BYTE_EN_W<CTRL2_SPEC> {
108 ECC_16TO18_BYTE_EN_W::new(self, 14)
109 }
110 #[doc = "Bits 25:30 - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY\\[5:0\\] + 1) MSPI core clock cycles."]
111 #[inline(always)]
112 pub fn cs_hold_delay(&mut self) -> CS_HOLD_DELAY_W<CTRL2_SPEC> {
113 CS_HOLD_DELAY_W::new(self, 25)
114 }
115 #[doc = "Bit 31 - The FSM will be reset."]
116 #[inline(always)]
117 pub fn sync_reset(&mut self) -> SYNC_RESET_W<CTRL2_SPEC> {
118 SYNC_RESET_W::new(self, 31)
119 }
120}
121#[doc = "SPI0 control 2 register.\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
122pub struct CTRL2_SPEC;
123impl crate::RegisterSpec for CTRL2_SPEC {
124 type Ux = u32;
125}
126#[doc = "`read()` method returns [`ctrl2::R`](R) reader structure"]
127impl crate::Readable for CTRL2_SPEC {}
128#[doc = "`write(|w| ..)` method takes [`ctrl2::W`](W) writer structure"]
129impl crate::Writable for CTRL2_SPEC {
130 type Safety = crate::Unsafe;
131 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
132 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
133}
134#[doc = "`reset()` method sets CTRL2 to value 0x2c21"]
135impl crate::Resettable for CTRL2_SPEC {
136 const RESET_VALUE: u32 = 0x2c21;
137}