1#[doc = "Register `SPI_SMEM_DDR` reader"]
2pub type R = crate::R<SPI_SMEM_DDR_SPEC>;
3#[doc = "Register `SPI_SMEM_DDR` writer"]
4pub type W = crate::W<SPI_SMEM_DDR_SPEC>;
5#[doc = "Field `EN` reader - 1: in ddr mode, 0 in sdr mode"]
6pub type EN_R = crate::BitReader;
7#[doc = "Field `EN` writer - 1: in ddr mode, 0 in sdr mode"]
8pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SPI_SMEM_VAR_DUMMY` reader - Set the bit to enable variable dummy cycle in spi ddr mode."]
10pub type SPI_SMEM_VAR_DUMMY_R = crate::BitReader;
11#[doc = "Field `SPI_SMEM_VAR_DUMMY` writer - Set the bit to enable variable dummy cycle in spi ddr mode."]
12pub type SPI_SMEM_VAR_DUMMY_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `RDAT_SWP` reader - Set the bit to reorder rx data of the word in spi ddr mode."]
14pub type RDAT_SWP_R = crate::BitReader;
15#[doc = "Field `RDAT_SWP` writer - Set the bit to reorder rx data of the word in spi ddr mode."]
16pub type RDAT_SWP_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `WDAT_SWP` reader - Set the bit to reorder tx data of the word in spi ddr mode."]
18pub type WDAT_SWP_R = crate::BitReader;
19#[doc = "Field `WDAT_SWP` writer - Set the bit to reorder tx data of the word in spi ddr mode."]
20pub type WDAT_SWP_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CMD_DIS` reader - the bit is used to disable dual edge in CMD phase when ddr mode."]
22pub type CMD_DIS_R = crate::BitReader;
23#[doc = "Field `CMD_DIS` writer - the bit is used to disable dual edge in CMD phase when ddr mode."]
24pub type CMD_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `SPI_SMEM_OUTMINBYTELEN` reader - It is the minimum output data length in the ddr psram."]
26pub type SPI_SMEM_OUTMINBYTELEN_R = crate::FieldReader;
27#[doc = "Field `SPI_SMEM_OUTMINBYTELEN` writer - It is the minimum output data length in the ddr psram."]
28pub type SPI_SMEM_OUTMINBYTELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
29#[doc = "Field `SPI_SMEM_TX_DDR_MSK_EN` reader - Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to external RAM."]
30pub type SPI_SMEM_TX_DDR_MSK_EN_R = crate::BitReader;
31#[doc = "Field `SPI_SMEM_TX_DDR_MSK_EN` writer - Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to external RAM."]
32pub type SPI_SMEM_TX_DDR_MSK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `SPI_SMEM_RX_DDR_MSK_EN` reader - Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to external RAM."]
34pub type SPI_SMEM_RX_DDR_MSK_EN_R = crate::BitReader;
35#[doc = "Field `SPI_SMEM_RX_DDR_MSK_EN` writer - Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to external RAM."]
36pub type SPI_SMEM_RX_DDR_MSK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `SPI_SMEM_USR_DDR_DQS_THD` reader - The delay number of data strobe which from memory based on SPI_CLK."]
38pub type SPI_SMEM_USR_DDR_DQS_THD_R = crate::FieldReader;
39#[doc = "Field `SPI_SMEM_USR_DDR_DQS_THD` writer - The delay number of data strobe which from memory based on SPI_CLK."]
40pub type SPI_SMEM_USR_DDR_DQS_THD_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
41#[doc = "Field `DQS_LOOP` reader - 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module"]
42pub type DQS_LOOP_R = crate::BitReader;
43#[doc = "Field `DQS_LOOP` writer - 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module"]
44pub type DQS_LOOP_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `DQS_LOOP_MODE` reader - When SPI_SMEM_DDR_DQS_LOOP and SPI_SMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active."]
46pub type DQS_LOOP_MODE_R = crate::BitReader;
47#[doc = "Field `DQS_LOOP_MODE` writer - When SPI_SMEM_DDR_DQS_LOOP and SPI_SMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active."]
48pub type DQS_LOOP_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `SPI_SMEM_CLK_DIFF_EN` reader - Set this bit to enable the differential SPI_CLK#."]
50pub type SPI_SMEM_CLK_DIFF_EN_R = crate::BitReader;
51#[doc = "Field `SPI_SMEM_CLK_DIFF_EN` writer - Set this bit to enable the differential SPI_CLK#."]
52pub type SPI_SMEM_CLK_DIFF_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `SPI_SMEM_HYPERBUS_MODE` reader - Set this bit to enable the SPI HyperBus mode."]
54pub type SPI_SMEM_HYPERBUS_MODE_R = crate::BitReader;
55#[doc = "Field `SPI_SMEM_HYPERBUS_MODE` writer - Set this bit to enable the SPI HyperBus mode."]
56pub type SPI_SMEM_HYPERBUS_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `SPI_SMEM_DQS_CA_IN` reader - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR."]
58pub type SPI_SMEM_DQS_CA_IN_R = crate::BitReader;
59#[doc = "Field `SPI_SMEM_DQS_CA_IN` writer - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR."]
60pub type SPI_SMEM_DQS_CA_IN_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `SPI_SMEM_HYPERBUS_DUMMY_2X` reader - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram."]
62pub type SPI_SMEM_HYPERBUS_DUMMY_2X_R = crate::BitReader;
63#[doc = "Field `SPI_SMEM_HYPERBUS_DUMMY_2X` writer - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram."]
64pub type SPI_SMEM_HYPERBUS_DUMMY_2X_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `SPI_SMEM_CLK_DIFF_INV` reader - Set this bit to invert SPI_DIFF when accesses to external RAM. ."]
66pub type SPI_SMEM_CLK_DIFF_INV_R = crate::BitReader;
67#[doc = "Field `SPI_SMEM_CLK_DIFF_INV` writer - Set this bit to invert SPI_DIFF when accesses to external RAM. ."]
68pub type SPI_SMEM_CLK_DIFF_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `SPI_SMEM_OCTA_RAM_ADDR` reader - Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[25:4\\], 6'd0, spi_usr_addr_value\\[3:1\\], 1'b0}."]
70pub type SPI_SMEM_OCTA_RAM_ADDR_R = crate::BitReader;
71#[doc = "Field `SPI_SMEM_OCTA_RAM_ADDR` writer - Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[25:4\\], 6'd0, spi_usr_addr_value\\[3:1\\], 1'b0}."]
72pub type SPI_SMEM_OCTA_RAM_ADDR_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `SPI_SMEM_HYPERBUS_CA` reader - Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[19:4\\], 13'd0, spi_usr_addr_value\\[3:1\\]}."]
74pub type SPI_SMEM_HYPERBUS_CA_R = crate::BitReader;
75#[doc = "Field `SPI_SMEM_HYPERBUS_CA` writer - Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[19:4\\], 13'd0, spi_usr_addr_value\\[3:1\\]}."]
76pub type SPI_SMEM_HYPERBUS_CA_W<'a, REG> = crate::BitWriter<'a, REG>;
77impl R {
78 #[doc = "Bit 0 - 1: in ddr mode, 0 in sdr mode"]
79 #[inline(always)]
80 pub fn en(&self) -> EN_R {
81 EN_R::new((self.bits & 1) != 0)
82 }
83 #[doc = "Bit 1 - Set the bit to enable variable dummy cycle in spi ddr mode."]
84 #[inline(always)]
85 pub fn spi_smem_var_dummy(&self) -> SPI_SMEM_VAR_DUMMY_R {
86 SPI_SMEM_VAR_DUMMY_R::new(((self.bits >> 1) & 1) != 0)
87 }
88 #[doc = "Bit 2 - Set the bit to reorder rx data of the word in spi ddr mode."]
89 #[inline(always)]
90 pub fn rdat_swp(&self) -> RDAT_SWP_R {
91 RDAT_SWP_R::new(((self.bits >> 2) & 1) != 0)
92 }
93 #[doc = "Bit 3 - Set the bit to reorder tx data of the word in spi ddr mode."]
94 #[inline(always)]
95 pub fn wdat_swp(&self) -> WDAT_SWP_R {
96 WDAT_SWP_R::new(((self.bits >> 3) & 1) != 0)
97 }
98 #[doc = "Bit 4 - the bit is used to disable dual edge in CMD phase when ddr mode."]
99 #[inline(always)]
100 pub fn cmd_dis(&self) -> CMD_DIS_R {
101 CMD_DIS_R::new(((self.bits >> 4) & 1) != 0)
102 }
103 #[doc = "Bits 5:11 - It is the minimum output data length in the ddr psram."]
104 #[inline(always)]
105 pub fn spi_smem_outminbytelen(&self) -> SPI_SMEM_OUTMINBYTELEN_R {
106 SPI_SMEM_OUTMINBYTELEN_R::new(((self.bits >> 5) & 0x7f) as u8)
107 }
108 #[doc = "Bit 12 - Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to external RAM."]
109 #[inline(always)]
110 pub fn spi_smem_tx_ddr_msk_en(&self) -> SPI_SMEM_TX_DDR_MSK_EN_R {
111 SPI_SMEM_TX_DDR_MSK_EN_R::new(((self.bits >> 12) & 1) != 0)
112 }
113 #[doc = "Bit 13 - Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to external RAM."]
114 #[inline(always)]
115 pub fn spi_smem_rx_ddr_msk_en(&self) -> SPI_SMEM_RX_DDR_MSK_EN_R {
116 SPI_SMEM_RX_DDR_MSK_EN_R::new(((self.bits >> 13) & 1) != 0)
117 }
118 #[doc = "Bits 14:20 - The delay number of data strobe which from memory based on SPI_CLK."]
119 #[inline(always)]
120 pub fn spi_smem_usr_ddr_dqs_thd(&self) -> SPI_SMEM_USR_DDR_DQS_THD_R {
121 SPI_SMEM_USR_DDR_DQS_THD_R::new(((self.bits >> 14) & 0x7f) as u8)
122 }
123 #[doc = "Bit 21 - 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module"]
124 #[inline(always)]
125 pub fn dqs_loop(&self) -> DQS_LOOP_R {
126 DQS_LOOP_R::new(((self.bits >> 21) & 1) != 0)
127 }
128 #[doc = "Bit 22 - When SPI_SMEM_DDR_DQS_LOOP and SPI_SMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active."]
129 #[inline(always)]
130 pub fn dqs_loop_mode(&self) -> DQS_LOOP_MODE_R {
131 DQS_LOOP_MODE_R::new(((self.bits >> 22) & 1) != 0)
132 }
133 #[doc = "Bit 24 - Set this bit to enable the differential SPI_CLK#."]
134 #[inline(always)]
135 pub fn spi_smem_clk_diff_en(&self) -> SPI_SMEM_CLK_DIFF_EN_R {
136 SPI_SMEM_CLK_DIFF_EN_R::new(((self.bits >> 24) & 1) != 0)
137 }
138 #[doc = "Bit 25 - Set this bit to enable the SPI HyperBus mode."]
139 #[inline(always)]
140 pub fn spi_smem_hyperbus_mode(&self) -> SPI_SMEM_HYPERBUS_MODE_R {
141 SPI_SMEM_HYPERBUS_MODE_R::new(((self.bits >> 25) & 1) != 0)
142 }
143 #[doc = "Bit 26 - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR."]
144 #[inline(always)]
145 pub fn spi_smem_dqs_ca_in(&self) -> SPI_SMEM_DQS_CA_IN_R {
146 SPI_SMEM_DQS_CA_IN_R::new(((self.bits >> 26) & 1) != 0)
147 }
148 #[doc = "Bit 27 - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram."]
149 #[inline(always)]
150 pub fn spi_smem_hyperbus_dummy_2x(&self) -> SPI_SMEM_HYPERBUS_DUMMY_2X_R {
151 SPI_SMEM_HYPERBUS_DUMMY_2X_R::new(((self.bits >> 27) & 1) != 0)
152 }
153 #[doc = "Bit 28 - Set this bit to invert SPI_DIFF when accesses to external RAM. ."]
154 #[inline(always)]
155 pub fn spi_smem_clk_diff_inv(&self) -> SPI_SMEM_CLK_DIFF_INV_R {
156 SPI_SMEM_CLK_DIFF_INV_R::new(((self.bits >> 28) & 1) != 0)
157 }
158 #[doc = "Bit 29 - Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[25:4\\], 6'd0, spi_usr_addr_value\\[3:1\\], 1'b0}."]
159 #[inline(always)]
160 pub fn spi_smem_octa_ram_addr(&self) -> SPI_SMEM_OCTA_RAM_ADDR_R {
161 SPI_SMEM_OCTA_RAM_ADDR_R::new(((self.bits >> 29) & 1) != 0)
162 }
163 #[doc = "Bit 30 - Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[19:4\\], 13'd0, spi_usr_addr_value\\[3:1\\]}."]
164 #[inline(always)]
165 pub fn spi_smem_hyperbus_ca(&self) -> SPI_SMEM_HYPERBUS_CA_R {
166 SPI_SMEM_HYPERBUS_CA_R::new(((self.bits >> 30) & 1) != 0)
167 }
168}
169#[cfg(feature = "impl-register-debug")]
170impl core::fmt::Debug for R {
171 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
172 f.debug_struct("SPI_SMEM_DDR")
173 .field("en", &self.en())
174 .field("spi_smem_var_dummy", &self.spi_smem_var_dummy())
175 .field("rdat_swp", &self.rdat_swp())
176 .field("wdat_swp", &self.wdat_swp())
177 .field("cmd_dis", &self.cmd_dis())
178 .field("spi_smem_outminbytelen", &self.spi_smem_outminbytelen())
179 .field("spi_smem_tx_ddr_msk_en", &self.spi_smem_tx_ddr_msk_en())
180 .field("spi_smem_rx_ddr_msk_en", &self.spi_smem_rx_ddr_msk_en())
181 .field("spi_smem_usr_ddr_dqs_thd", &self.spi_smem_usr_ddr_dqs_thd())
182 .field("dqs_loop", &self.dqs_loop())
183 .field("dqs_loop_mode", &self.dqs_loop_mode())
184 .field("spi_smem_clk_diff_en", &self.spi_smem_clk_diff_en())
185 .field("spi_smem_hyperbus_mode", &self.spi_smem_hyperbus_mode())
186 .field("spi_smem_dqs_ca_in", &self.spi_smem_dqs_ca_in())
187 .field(
188 "spi_smem_hyperbus_dummy_2x",
189 &self.spi_smem_hyperbus_dummy_2x(),
190 )
191 .field("spi_smem_clk_diff_inv", &self.spi_smem_clk_diff_inv())
192 .field("spi_smem_octa_ram_addr", &self.spi_smem_octa_ram_addr())
193 .field("spi_smem_hyperbus_ca", &self.spi_smem_hyperbus_ca())
194 .finish()
195 }
196}
197impl W {
198 #[doc = "Bit 0 - 1: in ddr mode, 0 in sdr mode"]
199 #[inline(always)]
200 pub fn en(&mut self) -> EN_W<SPI_SMEM_DDR_SPEC> {
201 EN_W::new(self, 0)
202 }
203 #[doc = "Bit 1 - Set the bit to enable variable dummy cycle in spi ddr mode."]
204 #[inline(always)]
205 pub fn spi_smem_var_dummy(&mut self) -> SPI_SMEM_VAR_DUMMY_W<SPI_SMEM_DDR_SPEC> {
206 SPI_SMEM_VAR_DUMMY_W::new(self, 1)
207 }
208 #[doc = "Bit 2 - Set the bit to reorder rx data of the word in spi ddr mode."]
209 #[inline(always)]
210 pub fn rdat_swp(&mut self) -> RDAT_SWP_W<SPI_SMEM_DDR_SPEC> {
211 RDAT_SWP_W::new(self, 2)
212 }
213 #[doc = "Bit 3 - Set the bit to reorder tx data of the word in spi ddr mode."]
214 #[inline(always)]
215 pub fn wdat_swp(&mut self) -> WDAT_SWP_W<SPI_SMEM_DDR_SPEC> {
216 WDAT_SWP_W::new(self, 3)
217 }
218 #[doc = "Bit 4 - the bit is used to disable dual edge in CMD phase when ddr mode."]
219 #[inline(always)]
220 pub fn cmd_dis(&mut self) -> CMD_DIS_W<SPI_SMEM_DDR_SPEC> {
221 CMD_DIS_W::new(self, 4)
222 }
223 #[doc = "Bits 5:11 - It is the minimum output data length in the ddr psram."]
224 #[inline(always)]
225 pub fn spi_smem_outminbytelen(&mut self) -> SPI_SMEM_OUTMINBYTELEN_W<SPI_SMEM_DDR_SPEC> {
226 SPI_SMEM_OUTMINBYTELEN_W::new(self, 5)
227 }
228 #[doc = "Bit 12 - Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to external RAM."]
229 #[inline(always)]
230 pub fn spi_smem_tx_ddr_msk_en(&mut self) -> SPI_SMEM_TX_DDR_MSK_EN_W<SPI_SMEM_DDR_SPEC> {
231 SPI_SMEM_TX_DDR_MSK_EN_W::new(self, 12)
232 }
233 #[doc = "Bit 13 - Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to external RAM."]
234 #[inline(always)]
235 pub fn spi_smem_rx_ddr_msk_en(&mut self) -> SPI_SMEM_RX_DDR_MSK_EN_W<SPI_SMEM_DDR_SPEC> {
236 SPI_SMEM_RX_DDR_MSK_EN_W::new(self, 13)
237 }
238 #[doc = "Bits 14:20 - The delay number of data strobe which from memory based on SPI_CLK."]
239 #[inline(always)]
240 pub fn spi_smem_usr_ddr_dqs_thd(&mut self) -> SPI_SMEM_USR_DDR_DQS_THD_W<SPI_SMEM_DDR_SPEC> {
241 SPI_SMEM_USR_DDR_DQS_THD_W::new(self, 14)
242 }
243 #[doc = "Bit 21 - 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module"]
244 #[inline(always)]
245 pub fn dqs_loop(&mut self) -> DQS_LOOP_W<SPI_SMEM_DDR_SPEC> {
246 DQS_LOOP_W::new(self, 21)
247 }
248 #[doc = "Bit 22 - When SPI_SMEM_DDR_DQS_LOOP and SPI_SMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active."]
249 #[inline(always)]
250 pub fn dqs_loop_mode(&mut self) -> DQS_LOOP_MODE_W<SPI_SMEM_DDR_SPEC> {
251 DQS_LOOP_MODE_W::new(self, 22)
252 }
253 #[doc = "Bit 24 - Set this bit to enable the differential SPI_CLK#."]
254 #[inline(always)]
255 pub fn spi_smem_clk_diff_en(&mut self) -> SPI_SMEM_CLK_DIFF_EN_W<SPI_SMEM_DDR_SPEC> {
256 SPI_SMEM_CLK_DIFF_EN_W::new(self, 24)
257 }
258 #[doc = "Bit 25 - Set this bit to enable the SPI HyperBus mode."]
259 #[inline(always)]
260 pub fn spi_smem_hyperbus_mode(&mut self) -> SPI_SMEM_HYPERBUS_MODE_W<SPI_SMEM_DDR_SPEC> {
261 SPI_SMEM_HYPERBUS_MODE_W::new(self, 25)
262 }
263 #[doc = "Bit 26 - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR."]
264 #[inline(always)]
265 pub fn spi_smem_dqs_ca_in(&mut self) -> SPI_SMEM_DQS_CA_IN_W<SPI_SMEM_DDR_SPEC> {
266 SPI_SMEM_DQS_CA_IN_W::new(self, 26)
267 }
268 #[doc = "Bit 27 - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram."]
269 #[inline(always)]
270 pub fn spi_smem_hyperbus_dummy_2x(
271 &mut self,
272 ) -> SPI_SMEM_HYPERBUS_DUMMY_2X_W<SPI_SMEM_DDR_SPEC> {
273 SPI_SMEM_HYPERBUS_DUMMY_2X_W::new(self, 27)
274 }
275 #[doc = "Bit 28 - Set this bit to invert SPI_DIFF when accesses to external RAM. ."]
276 #[inline(always)]
277 pub fn spi_smem_clk_diff_inv(&mut self) -> SPI_SMEM_CLK_DIFF_INV_W<SPI_SMEM_DDR_SPEC> {
278 SPI_SMEM_CLK_DIFF_INV_W::new(self, 28)
279 }
280 #[doc = "Bit 29 - Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[25:4\\], 6'd0, spi_usr_addr_value\\[3:1\\], 1'b0}."]
281 #[inline(always)]
282 pub fn spi_smem_octa_ram_addr(&mut self) -> SPI_SMEM_OCTA_RAM_ADDR_W<SPI_SMEM_DDR_SPEC> {
283 SPI_SMEM_OCTA_RAM_ADDR_W::new(self, 29)
284 }
285 #[doc = "Bit 30 - Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[19:4\\], 13'd0, spi_usr_addr_value\\[3:1\\]}."]
286 #[inline(always)]
287 pub fn spi_smem_hyperbus_ca(&mut self) -> SPI_SMEM_HYPERBUS_CA_W<SPI_SMEM_DDR_SPEC> {
288 SPI_SMEM_HYPERBUS_CA_W::new(self, 30)
289 }
290}
291#[doc = "SPI0 external RAM DDR mode control register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_smem_ddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_smem_ddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
292pub struct SPI_SMEM_DDR_SPEC;
293impl crate::RegisterSpec for SPI_SMEM_DDR_SPEC {
294 type Ux = u32;
295}
296#[doc = "`read()` method returns [`spi_smem_ddr::R`](R) reader structure"]
297impl crate::Readable for SPI_SMEM_DDR_SPEC {}
298#[doc = "`write(|w| ..)` method takes [`spi_smem_ddr::W`](W) writer structure"]
299impl crate::Writable for SPI_SMEM_DDR_SPEC {
300 type Safety = crate::Unsafe;
301 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
302 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
303}
304#[doc = "`reset()` method sets SPI_SMEM_DDR to value 0x3020"]
305impl crate::Resettable for SPI_SMEM_DDR_SPEC {
306 const RESET_VALUE: u32 = 0x3020;
307}