esp32s3/apb_saradc/
int_raw.rs

1#[doc = "Register `INT_RAW` reader"]
2pub type R = crate::R<INT_RAW_SPEC>;
3#[doc = "Field `THRES1_LOW` reader - interrupt of thres1 low"]
4pub type THRES1_LOW_R = crate::BitReader;
5#[doc = "Field `THRES0_LOW` reader - interrupt of thres0 low"]
6pub type THRES0_LOW_R = crate::BitReader;
7#[doc = "Field `THRES1_HIGH` reader - interrupt of thres1 high"]
8pub type THRES1_HIGH_R = crate::BitReader;
9#[doc = "Field `THRES0_HIGH` reader - interrupt of thres0 high"]
10pub type THRES0_HIGH_R = crate::BitReader;
11#[doc = "Field `ADC2_DONE` reader - interrupt of sar2 done"]
12pub type ADC2_DONE_R = crate::BitReader;
13#[doc = "Field `ADC1_DONE` reader - interrupt of sar1 done"]
14pub type ADC1_DONE_R = crate::BitReader;
15impl R {
16    #[doc = "Bit 26 - interrupt of thres1 low"]
17    #[inline(always)]
18    pub fn thres1_low(&self) -> THRES1_LOW_R {
19        THRES1_LOW_R::new(((self.bits >> 26) & 1) != 0)
20    }
21    #[doc = "Bit 27 - interrupt of thres0 low"]
22    #[inline(always)]
23    pub fn thres0_low(&self) -> THRES0_LOW_R {
24        THRES0_LOW_R::new(((self.bits >> 27) & 1) != 0)
25    }
26    #[doc = "Bit 28 - interrupt of thres1 high"]
27    #[inline(always)]
28    pub fn thres1_high(&self) -> THRES1_HIGH_R {
29        THRES1_HIGH_R::new(((self.bits >> 28) & 1) != 0)
30    }
31    #[doc = "Bit 29 - interrupt of thres0 high"]
32    #[inline(always)]
33    pub fn thres0_high(&self) -> THRES0_HIGH_R {
34        THRES0_HIGH_R::new(((self.bits >> 29) & 1) != 0)
35    }
36    #[doc = "Bit 30 - interrupt of sar2 done"]
37    #[inline(always)]
38    pub fn adc2_done(&self) -> ADC2_DONE_R {
39        ADC2_DONE_R::new(((self.bits >> 30) & 1) != 0)
40    }
41    #[doc = "Bit 31 - interrupt of sar1 done"]
42    #[inline(always)]
43    pub fn adc1_done(&self) -> ADC1_DONE_R {
44        ADC1_DONE_R::new(((self.bits >> 31) & 1) != 0)
45    }
46}
47#[cfg(feature = "impl-register-debug")]
48impl core::fmt::Debug for R {
49    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
50        f.debug_struct("INT_RAW")
51            .field("thres1_low", &self.thres1_low())
52            .field("thres0_low", &self.thres0_low())
53            .field("thres1_high", &self.thres1_high())
54            .field("thres0_high", &self.thres0_high())
55            .field("adc2_done", &self.adc2_done())
56            .field("adc1_done", &self.adc1_done())
57            .finish()
58    }
59}
60#[doc = "raw of interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
61pub struct INT_RAW_SPEC;
62impl crate::RegisterSpec for INT_RAW_SPEC {
63    type Ux = u32;
64}
65#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"]
66impl crate::Readable for INT_RAW_SPEC {}
67#[doc = "`reset()` method sets INT_RAW to value 0"]
68impl crate::Resettable for INT_RAW_SPEC {
69    const RESET_VALUE: u32 = 0;
70}
esp32s3/apb_saradc/int_raw.rs

esp32s3/apb_saradc/
int_raw.rs
