esp32s3/uart0/
fifo.rs

1#[doc = "Register `FIFO` reader"]
2pub type R = crate::R<FIFO_SPEC>;
3#[doc = "Register `FIFO` writer"]
4pub type W = crate::W<FIFO_SPEC>;
5#[doc = "Field `RXFIFO_RD_BYTE` reader - UART 0 accesses FIFO via this register."]
6pub type RXFIFO_RD_BYTE_R = crate::FieldReader;
7#[doc = "Field `RXFIFO_RD_BYTE` writer - UART 0 accesses FIFO via this register."]
8pub type RXFIFO_RD_BYTE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9impl R {
10    #[doc = "Bits 0:7 - UART 0 accesses FIFO via this register."]
11    #[inline(always)]
12    pub fn rxfifo_rd_byte(&self) -> RXFIFO_RD_BYTE_R {
13        RXFIFO_RD_BYTE_R::new((self.bits & 0xff) as u8)
14    }
15}
16#[cfg(feature = "impl-register-debug")]
17impl core::fmt::Debug for R {
18    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19        f.debug_struct("FIFO")
20            .field("rxfifo_rd_byte", &self.rxfifo_rd_byte())
21            .finish()
22    }
23}
24impl W {
25    #[doc = "Bits 0:7 - UART 0 accesses FIFO via this register."]
26    #[inline(always)]
27    pub fn rxfifo_rd_byte(&mut self) -> RXFIFO_RD_BYTE_W<FIFO_SPEC> {
28        RXFIFO_RD_BYTE_W::new(self, 0)
29    }
30}
31#[doc = "FIFO data register\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
32pub struct FIFO_SPEC;
33impl crate::RegisterSpec for FIFO_SPEC {
34    type Ux = u32;
35}
36#[doc = "`read()` method returns [`fifo::R`](R) reader structure"]
37impl crate::Readable for FIFO_SPEC {}
38#[doc = "`write(|w| ..)` method takes [`fifo::W`](W) writer structure"]
39impl crate::Writable for FIFO_SPEC {
40    type Safety = crate::Unsafe;
41}
42#[doc = "`reset()` method sets FIFO to value 0"]
43impl crate::Resettable for FIFO_SPEC {}
esp32s3/uart0/fifo.rs

esp32s3/uart0/
fifo.rs
