Module esp32s3::uart0::int_st

Masked interrupt status

Structs

INT_ST_SPEC

Masked interrupt status

R

Register INT_ST reader

Type Definitions

AT_CMD_CHAR_DET_INT_ST_R

Field AT_CMD_CHAR_DET_INT_ST reader - This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.

BRK_DET_INT_ST_R

Field BRK_DET_INT_ST reader - This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.

CTS_CHG_INT_ST_R

Field CTS_CHG_INT_ST reader - This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.

DSR_CHG_INT_ST_R

Field DSR_CHG_INT_ST reader - This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.

FRM_ERR_INT_ST_R

Field FRM_ERR_INT_ST reader - This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.

GLITCH_DET_INT_ST_R

Field GLITCH_DET_INT_ST reader - This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.

PARITY_ERR_INT_ST_R

Field PARITY_ERR_INT_ST reader - This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.

RS485_CLASH_INT_ST_R

Field RS485_CLASH_INT_ST reader - This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.

RS485_FRM_ERR_INT_ST_R

Field RS485_FRM_ERR_INT_ST reader - This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.

RS485_PARITY_ERR_INT_ST_R

Field RS485_PARITY_ERR_INT_ST reader - This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.

RXFIFO_FULL_INT_ST_R

Field RXFIFO_FULL_INT_ST reader - This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.

RXFIFO_OVF_INT_ST_R

Field RXFIFO_OVF_INT_ST reader - This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.

RXFIFO_TOUT_INT_ST_R

Field RXFIFO_TOUT_INT_ST reader - This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.

SW_XOFF_INT_ST_R

Field SW_XOFF_INT_ST reader - This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.

SW_XON_INT_ST_R

Field SW_XON_INT_ST reader - This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.

TXFIFO_EMPTY_INT_ST_R

Field TXFIFO_EMPTY_INT_ST reader - This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1.

TX_BRK_DONE_INT_ST_R

Field TX_BRK_DONE_INT_ST reader - This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.

TX_BRK_IDLE_DONE_INT_ST_R

Field TX_BRK_IDLE_DONE_INT_ST reader - This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.

TX_DONE_INT_ST_R

Field TX_DONE_INT_ST reader - This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.

WAKEUP_INT_ST_R

Field WAKEUP_INT_ST reader - This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.