Module esp32s3::spi2::slave

SPI slave control register

Structs

R

Register SLAVE reader

SLAVE_SPEC

SPI slave control register

W

Register SLAVE writer

Type Definitions

CLK_MODE_13_R

Field CLK_MODE_13 reader - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].

CLK_MODE_13_W

Field CLK_MODE_13 writer - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].

CLK_MODE_R

Field CLK_MODE reader - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.

CLK_MODE_W

Field CLK_MODE writer - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.

DMA_SEG_MAGIC_VALUE_R

Field DMA_SEG_MAGIC_VALUE reader - The magic value of BM table in master DMA seg-trans.

DMA_SEG_MAGIC_VALUE_W

Field DMA_SEG_MAGIC_VALUE writer - The magic value of BM table in master DMA seg-trans.

MODE_R

Field MODE reader - Set SPI work mode. 1: slave mode 0: master mode.

MODE_W

Field MODE writer - Set SPI work mode. 1: slave mode 0: master mode.

RSCK_DATA_OUT_R

Field RSCK_DATA_OUT reader - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge

RSCK_DATA_OUT_W

Field RSCK_DATA_OUT writer - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge

SLV_RDBUF_BITLEN_EN_R

Field SLV_RDBUF_BITLEN_EN reader - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others

SLV_RDBUF_BITLEN_EN_W

Field SLV_RDBUF_BITLEN_EN writer - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others

SLV_RDDMA_BITLEN_EN_R

Field SLV_RDDMA_BITLEN_EN reader - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others

SLV_RDDMA_BITLEN_EN_W

Field SLV_RDDMA_BITLEN_EN writer - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others

SLV_WRBUF_BITLEN_EN_R

Field SLV_WRBUF_BITLEN_EN reader - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others

SLV_WRBUF_BITLEN_EN_W

Field SLV_WRBUF_BITLEN_EN writer - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others

SLV_WRDMA_BITLEN_EN_R

Field SLV_WRDMA_BITLEN_EN reader - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others

SLV_WRDMA_BITLEN_EN_W

Field SLV_WRDMA_BITLEN_EN writer - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others

SOFT_RESET_W

Field SOFT_RESET writer - Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.

USR_CONF_R

Field USR_CONF reader - 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.

USR_CONF_W

Field USR_CONF writer - 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.