Module esp32s3::spi0::ctrl1

SPI0 control 1 register.

Structs

CTRL1_SPEC

SPI0 control 1 register.

R

Register CTRL1 reader

W

Register CTRL1 writer

Type Definitions

CLK_MODE_R

Field CLK_MODE reader - SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on.

CLK_MODE_W

Field CLK_MODE writer - SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on.

RXFIFO_RST_R

Field RXFIFO_RST reader - SPI0 RX FIFO reset signal. Set this bit and clear it before SPI0 transfer starts.

RXFIFO_RST_W

Field RXFIFO_RST writer - SPI0 RX FIFO reset signal. Set this bit and clear it before SPI0 transfer starts.