Expand description

Power configuration register

Structs

Register SCL_SP_CONF reader
Power configuration register
Register SCL_SP_CONF writer

Type Definitions

Field SCL_PD_EN reader - The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low.
Field SCL_PD_EN writer - The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low.
Field SCL_RST_SLV_EN reader - When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0].
Field SCL_RST_SLV_EN writer - When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0].
Field SCL_RST_SLV_NUM reader - Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1.
Field SCL_RST_SLV_NUM writer - Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1.
Field SDA_PD_EN reader - The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low.
Field SDA_PD_EN writer - The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low.