esp32s3/extmem/
dcache_prelock_ctrl.rs

1#[doc = "Register `DCACHE_PRELOCK_CTRL` reader"]
2pub type R = crate::R<DCACHE_PRELOCK_CTRL_SPEC>;
3#[doc = "Register `DCACHE_PRELOCK_CTRL` writer"]
4pub type W = crate::W<DCACHE_PRELOCK_CTRL_SPEC>;
5#[doc = "Field `DCACHE_PRELOCK_SCT0_EN` reader - The bit is used to enable the first section of prelock function."]
6pub type DCACHE_PRELOCK_SCT0_EN_R = crate::BitReader;
7#[doc = "Field `DCACHE_PRELOCK_SCT0_EN` writer - The bit is used to enable the first section of prelock function."]
8pub type DCACHE_PRELOCK_SCT0_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `DCACHE_PRELOCK_SCT1_EN` reader - The bit is used to enable the second section of prelock function."]
10pub type DCACHE_PRELOCK_SCT1_EN_R = crate::BitReader;
11#[doc = "Field `DCACHE_PRELOCK_SCT1_EN` writer - The bit is used to enable the second section of prelock function."]
12pub type DCACHE_PRELOCK_SCT1_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13impl R {
14    #[doc = "Bit 0 - The bit is used to enable the first section of prelock function."]
15    #[inline(always)]
16    pub fn dcache_prelock_sct0_en(&self) -> DCACHE_PRELOCK_SCT0_EN_R {
17        DCACHE_PRELOCK_SCT0_EN_R::new((self.bits & 1) != 0)
18    }
19    #[doc = "Bit 1 - The bit is used to enable the second section of prelock function."]
20    #[inline(always)]
21    pub fn dcache_prelock_sct1_en(&self) -> DCACHE_PRELOCK_SCT1_EN_R {
22        DCACHE_PRELOCK_SCT1_EN_R::new(((self.bits >> 1) & 1) != 0)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("DCACHE_PRELOCK_CTRL")
29            .field("dcache_prelock_sct0_en", &self.dcache_prelock_sct0_en())
30            .field("dcache_prelock_sct1_en", &self.dcache_prelock_sct1_en())
31            .finish()
32    }
33}
34impl W {
35    #[doc = "Bit 0 - The bit is used to enable the first section of prelock function."]
36    #[inline(always)]
37    pub fn dcache_prelock_sct0_en(&mut self) -> DCACHE_PRELOCK_SCT0_EN_W<DCACHE_PRELOCK_CTRL_SPEC> {
38        DCACHE_PRELOCK_SCT0_EN_W::new(self, 0)
39    }
40    #[doc = "Bit 1 - The bit is used to enable the second section of prelock function."]
41    #[inline(always)]
42    pub fn dcache_prelock_sct1_en(&mut self) -> DCACHE_PRELOCK_SCT1_EN_W<DCACHE_PRELOCK_CTRL_SPEC> {
43        DCACHE_PRELOCK_SCT1_EN_W::new(self, 1)
44    }
45}
46#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`dcache_prelock_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcache_prelock_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
47pub struct DCACHE_PRELOCK_CTRL_SPEC;
48impl crate::RegisterSpec for DCACHE_PRELOCK_CTRL_SPEC {
49    type Ux = u32;
50}
51#[doc = "`read()` method returns [`dcache_prelock_ctrl::R`](R) reader structure"]
52impl crate::Readable for DCACHE_PRELOCK_CTRL_SPEC {}
53#[doc = "`write(|w| ..)` method takes [`dcache_prelock_ctrl::W`](W) writer structure"]
54impl crate::Writable for DCACHE_PRELOCK_CTRL_SPEC {
55    type Safety = crate::Unsafe;
56}
57#[doc = "`reset()` method sets DCACHE_PRELOCK_CTRL to value 0"]
58impl crate::Resettable for DCACHE_PRELOCK_CTRL_SPEC {}
esp32s3/extmem/dcache_prelock_ctrl.rs

esp32s3/extmem/
dcache_prelock_ctrl.rs
